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june 2009 doc id 12321 rev 5 1/247 1 st72344xx st72345xx 8-bit mcu with up to 16 kbyt es flash memory, 10-bit adc, two 16-bit timers, two i2c, spi, sci features memories ? up to 16 kbytes program memory: single voltage extended flash (xflash) with read- out and write protection, in-circuit and in- application programming (icp and iap). 10k write/erase cycles guaranteed, data retention: 20 years at 55 c. ? up to 1 kbyte ram ? 256 bytes data eeprom with readout protection. 300k write/erase cycles guaranteed, data retention: 20 years at 55 c. clock, reset and supply management ? power on / power off safe reset with 3 programmable threshold levels (lvd) ? auxiliary voltage detector (avd) ? clock sources: crys tal/ceramic resonator oscillators, high-accuracy internal rc oscillator or external clock ? pll for 4x or 8x frequency multiplication ? 5 power-saving modes: slow, wait, halt, auto-wakeup from halt and active-halt ? clock output capability (f cpu ) interrupt management ? nested interrupt controller ? 10 interrupt vectors plus trap and reset ? 9 external interrupt lines on 4 vectors up to 34 i/o ports ? up to 34 multifunctional bidirectional i/o lines ? up to 12 high sink outputs (10 on 32-pin devices) 4 timers ? configurable window watchdog timer ?real-time base ? 16-bit timer a with: 1 input capture, 1 output compares, external clock input, pwm and pulse generator modes ? 16-bit timer b with: 2 input captures, 2 output compares, pwm and pulse generator modes 3 communication interfaces ?i 2 c multimaster / slave ?i 2 c slave 3 addresses no stretch with dma access and byte pair coherency on i2c read ? sci asynchronous serial interface (lin compatible) ? spi synchronous serial interface 1 analog peripheral ? 10-bit adc with 12 input channels (8 on 32- pin devices) instruction set ? 8-bit data manipulation ? 63 basic instructions with illegal opcode detection ? 17 main addressing modes ? 8 x 8 unsigned multiply instruction development tools ? full hardware/software development package ? on-chip debug module table 1. device summary references part numbers st72344xx st72344k2, st72344k4, st72344s2, st72344s4 st72345xx st72345c4 lqfp48 7 x 7 mm lqfp44 lqfp32 7 7 mm 10 10 mm www.st.com
contents st72344xx st72345xx 2/247 doc id 12321 rev 5 contents 1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3 register and memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4 flash program memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 4.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 4.2 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 4.3 programming modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 4.3.1 in-circuit programming (icp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 4.3.2 in-application programming (iap) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 4.4 icc interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 4.5 memory protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 4.5.1 readout protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 4.5.2 flash write/erase protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 4.6 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 4.6.1 flash control/status register (fcsr) . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 5 data eeprom . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 5.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 5.2 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 5.3 memory access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 5.4 power saving modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5.4.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5.4.2 active-halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5.4.3 halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5.5 access error handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5.6 data eeprom readout protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 5.7 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 5.7.1 eeprom control/status regi ster (eecsr) . . . . . . . . . . . . . . . . . . . . . . 35 6 central processing unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
st72344xx st72345xx contents doc id 12321 rev 5 3/247 6.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 6.2 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 6.3 cpu registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 6.3.1 condition code register (cc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 6.3.2 stack pointer (sp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 7 supply, reset and clock management . . . . . . . . . . . . . . . . . . . . . . . . . . 41 7.1 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 7.2 phase locked loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 7.3 multioscillator (mo) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 7.3.1 external clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 7.3.2 crystal/ceramic oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 7.3.3 internal rc oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 7.4 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 7.4.1 rc control register (rccrh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 7.4.2 rc control register (rccrl) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 7.5 reset sequence manager (rsm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 7.5.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 7.5.2 asynchronous external reset pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 7.5.3 external power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 7.5.4 internal low-voltage detector (lvd) reset . . . . . . . . . . . . . . . . . . . . . . . . 48 7.5.5 internal watchdog reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 7.6 system integrity management (si) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 7.6.1 low-voltage detector (lvd) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 7.6.2 auxiliary-voltage detector (avd) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 7.6.3 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 7.6.4 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 7.6.5 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 8 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 8.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 8.2 masking and processing flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 8.3 interrupts and low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 8.4 concurrent & nested management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 8.5 interrupt register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 8.5.1 cpu cc register interrupt bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
contents st72344xx st72345xx 4/247 doc id 12321 rev 5 8.5.2 interrupt software priority registers (isprx) . . . . . . . . . . . . . . . . . . . . . 58 8.6 external interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 8.6.1 i/o port interrupt sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 8.7 external interrupt control register (eicr) . . . . . . . . . . . . . . . . . . . . . . . . . 61 9 power-saving modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 9.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 9.2 slow mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 9.3 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 9.4 halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 9.5 active-halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 9.6 auto-wakeup from halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 9.7 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 9.7.1 awufh control/status register (awucsr) . . . . . . . . . . . . . . . . . . . . . . 72 9.7.2 awufh prescaler register (awupr) . . . . . . . . . . . . . . . . . . . . . . . . . . 73 10 i/o ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 10.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 10.2 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 10.2.1 input modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 10.2.2 output modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 10.2.3 alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 10.3 i/o port implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 10.4 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 10.5 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 10.5.1 i/o port implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 11 on-chip peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 11.1 window watchdog (wwdg) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 11.1.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 11.1.2 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 11.1.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 11.1.4 using halt mode with the wdg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 11.1.5 how to program the watchdog timeout . . . . . . . . . . . . . . . . . . . . . . . . . 84 11.1.6 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 11.1.7 hardware watchdog option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
st72344xx st72345xx contents doc id 12321 rev 5 5/247 11.1.8 using halt mode with the wdg (wdghalt option) . . . . . . . . . . . . . . . 87 11.1.9 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 11.1.10 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 11.2 main clock controller with real-time clock and beeper (mcc/rtc) . . . . . 88 11.2.1 programmable cpu clock prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 11.2.2 clock-out capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 11.2.3 real-time clock timer (rtc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 11.2.4 beeper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 11.2.5 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 11.2.6 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 11.2.7 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 11.3 16-bit timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 11.3.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 11.3.2 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 11.3.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 11.3.4 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 11.3.5 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 11.3.6 summary of timer modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 11.3.7 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 11.4 serial peripheral interface (spi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 11.4.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 11.4.2 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 11.4.3 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 11.4.4 clock phase and clock polarity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 11.4.5 error flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 11.4.6 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 11.4.7 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 11.4.8 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 11.5 sci serial communication interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 11.5.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 11.5.2 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 11.5.3 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 11.5.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 11.5.5 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 11.5.6 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 11.5.7 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
contents st72344xx st72345xx 6/247 doc id 12321 rev 5 11.6 i2c bus interface (i2c) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 11.6.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 11.6.2 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 11.6.3 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 11.6.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 11.6.5 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 11.6.6 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 11.6.7 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 11.7 i2c triple slave interface with dma (i2c3s) . . . . . . . . . . . . . . . . . . . . . . 167 11.7.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 11.7.2 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 11.7.3 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 11.7.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 11.7.5 address handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 11.7.6 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 11.7.7 interrupt generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 11.7.8 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 11.8 10-bit a/d converter (adc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 11.8.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 11.8.2 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 11.8.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 11.8.4 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 11.8.5 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 11.8.6 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 12 instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 12.1 st7 addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 12.1.1 inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 12.1.2 immediate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 12.1.3 direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 12.1.4 indexed (no offset, short, long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 12.1.5 indirect (short, long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 12.1.6 indirect indexed (short, long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 12.1.7 relative mode (direct, indirect) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 12.2 instruction groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 12.2.1 illegal opcode reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
st72344xx st72345xx contents doc id 12321 rev 5 7/247 13 electrical characteristi cs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 13.1 parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 13.1.1 minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 13.1.2 typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 13.1.3 typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 13.1.4 loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 13.1.5 pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 13.2 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 13.3 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 13.4 internal rc oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 13.5 supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 13.6 clock and timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 13.6.1 crystal and ceramic resonator oscillators . . . . . . . . . . . . . . . . . . . . . . 210 13.7 memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 13.8 emc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 13.8.1 functional ems (ele ctromagnetic susc eptibility) . . . . . . . . . . . . . . . . . 213 13.8.2 emi (electromagnetic interference) . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 13.8.3 absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . 214 13.9 i/o port pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 13.10 control pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 13.10.1 asynchronous reset pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 13.11 communication interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . 224 13.11.1 i2c and i2c3sns interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 13.12 10-bit adc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 14 package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 14.1 ecopack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 14.2 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 15 device configuration and ordering informati on . . . . . . . . . . . . . . . . . 232 15.1 option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232 15.1.1 option byte 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232 15.1.2 option byte 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233 15.1.3 option byte 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234 15.1.4 option byte 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235
contents st72344xx st72345xx 8/247 doc id 12321 rev 5 15.2 device ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236 15.3 development tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236 15.3.1 starter kits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236 15.3.2 development and debugging tools . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 15.3.3 programming tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 15.3.4 order codes for st72f34x development tools . . . . . . . . . . . . . . . . . . 238 16 known limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239 16.1 external interrupt missed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239 16.1.1 workaround . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239 16.1.2 unexpected reset fetch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241 16.2 clearing active interrupts outside interrupt routine . . . . . . . . . . . . . . . . . 241 16.3 16-bit timer pwm mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242 16.4 timd set simultaneously with oc interrupt . . . . . . . . . . . . . . . . . . . . . . 242 16.4.1 impact on the application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242 16.4.2 workaround . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 16.5 sci wrong break duration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 16.5.1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 16.5.2 occurrence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 16.5.3 workaround . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 16.6 random read operations not supported with the standard i2c . . . . . . . 244 16.6.1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244 16.6.2 occurrence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244 16.6.3 workaround . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244 16.7 programming of eeprom data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244 16.7.1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244 16.7.2 impact on application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244 16.7.3 workaround . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244 17 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245
st72344xx st72345xx list of tables doc id 12321 rev 5 9/247 list of tables table 1. device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table 2. st72344xx and st72345xx features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 3. device pin description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 4. hardware register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 5. data eeprom register map and re set values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 6. interrupt software priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 7. pll configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 table 8. st7 clock sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 table 9. calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 table 10. low-power mode description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 table 11. interrupt event. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 table 12. lvdrf and wdgrf description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 table 13. interrupt software priority levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 table 14. interrupt software priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 table 15. interrupt vector addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 table 16. dedicated interrupt instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 table 17. interrupt mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 table 18. external interrupt sensitivity (ei2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 table 19. external interrupt sensitivity (ei3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 table 20. external interrupt sensitivity (ei0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 table 21. external interrupt sensitivity (ei1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 table 22. nested interrupts register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 table 23. power saving mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 table 24. awupr dividing factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 table 25. awu register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3 table 26. output modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 table 27. i/o port mode options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 table 28. i/o port configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 table 29. description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 table 30. description of interrupt events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 table 31. i/o port register configurations (standard ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 table 32. i/o port register configurations (interrupt ports with pull-up). . . . . . . . . . . . . . . . . . . . . . . . 79 table 33. i/o port register configurations (interrupt ports without pull-up) . . . . . . . . . . . . . . . . . . . . . 79 table 34. i/o port register configurations (true open drain ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 table 35. port configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 table 36. i/o port register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 table 37. descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 table 38. watchdog timer register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 table 39. mode description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 table 40. interrupt event. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 table 41. cpu clock prescaler selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 table 42. time base control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 table 43. beep control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 table 44. main clock controller register map and reset values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 table 45. icir register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 table 46. ocir register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 table 47. low-power mode description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 table 48. interrupt events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
list of tables st72344xx st72345xx 10/247 doc id 12321 rev 5 table 49. timer modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 table 50. clock control bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 table 51. 16-bit timer register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 table 52. description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 table 53. interrupt events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 table 54. spi master mode sck frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 table 55. spi register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 table 56. frame formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 table 57. mode description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 table 58. interrupt events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 table 59. scp[1:0] configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 table 60. sct[2:0] configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 table 61. scr[2:0] configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 table 62. baud rate selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 table 63. sci register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 49 table 64. mode description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 table 65. interrupt events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 table 66. fr[1:0] configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 table 67. i2c register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 table 68. mode description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 table 69. interrupt events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 table 70. pl configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 table 71. i2c3s register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 table 72. mode description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 table 73. channel selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 table 74. adc register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 9 table 75. addressing mode groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 table 76. st7 addressing mode overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 0 table 77. inherent instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 table 78. immediate instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 table 79. instructions supporting direct, indexed, in direct and indirect indexed addressing modes 194 table 80. short instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 table 81. relative direct/indirect instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 table 82. main instruction groups. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 table 83. illegal opcode detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 table 84. voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 table 85. current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 table 86. thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 table 87. general operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 table 88. lvd thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 table 89. avd thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 table 90. pll characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 table 91. internal rc oscilla tor and pll . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 table 92. internal rc oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 table 93. supply current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 table 94. on-chip peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 table 95. general timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 table 96. external clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 table 97. auto-wakeup from ha lt oscillator (awu) characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 210 table 98. crystal/ceramic resonator oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 table 99. recommended load capacitance vs. equivalent serial resistance of ceramic resonator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
st72344xx st72345xx list of tables doc id 12321 rev 5 11/247 table 100. ram and hardware registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 table 101. flash program memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 table 102. eeprom data memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 table 103. ems test results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 table 104. emi emissions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 table 105. esd absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 14 table 106. electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 table 107. general characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 table 108. output driving current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 table 109. asynchronous reset pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 table 110. i2c and i2c3sns interfaces characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 table 111. scl frequency table (multimaster i 2 c interface) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 table 112. adc accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 table 113. adc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226 table 114. 32-pin low profile quad flat package (7 x 7 mm) mechanical data . . . . . . . . . . . . . . . . . . 228 table 115. 40-lead very thin fine pitch quad flat no-lead package mechanical data . . . . . . . . . . . . . 229 table 116. 44-pin low profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . 230 table 117. 48-pin low profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . 231 table 118. thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231 table 119. lvd threshold configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232 table 120. size of sector 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232 table 121. selection of th e resonator oscillator range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4 table 122. list of valid option combinations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234 table 123. package selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235 table 124. option byte default values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235 table 126. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245
list of figures st72344xx st72345xx 12/247 doc id 12321 rev 5 list of figures figure 1. general block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 2. lqfp32 package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 3. lqfp44 package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 4. lqfp48 package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 5. memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 6. typical icc interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 7. eeprom block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 figure 8. data eeprom programmin g flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 figure 9. data eeprom write operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 figure 10. data eeprom programming cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 11. cpu registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 figure 12. stack manipulation example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 figure 13. clock, reset and supply block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 figure 14. pll output frequency timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 figure 15. reset sequence phases. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 figure 16. reset block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 figure 17. reset sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 figure 18. low voltage detector vs. reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 figure 19. using the avd to monitor vdd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 figure 20. interrupt processing flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 figure 21. priority decision process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 figure 22. concurrent interrupt management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 figure 23. nested interrupt management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 figure 24. external interrupt control bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 figure 25. power saving mode transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 figure 26. slow mode clock transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 figure 27. wait mode flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 figure 28. halt timing overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 figure 29. halt mode flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 figure 30. active-halt timing overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 figure 31. active-halt mode flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 figure 32. awufh mode block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 figure 33. awuf halt timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 figure 34. awufh mode flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 figure 35. i/o port general block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 figure 36. interrupt i/o port state transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 figure 37. watchdog block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 figure 38. approximate timeout duration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 figure 39. exact timeout duration (tmin and tmax) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 figure 40. window watchdog timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 figure 41. main clock controller (mcc/rtc) block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 figure 42. timer block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 figure 43. 16-bit read sequence (from either the counter register or the alternate counter register) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 figure 44. counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 figure 45. counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 figure 46. counter timing diagram, internal clock divided by 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 figure 47. input capture block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
st72344xx st72345xx list of figures doc id 12321 rev 5 13/247 figure 48. input capture timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 figure 49. output compare block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 figure 50. output compare timing diagram, f timer = f cpu /2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 figure 51. output compare timing diagram, f timer = f cpu /4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 figure 52. one-pulse mode cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 figure 53. one-pulse mode timing example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 04 figure 54. pulse width modulation mode timing example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 figure 55. pulse width modulation cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 figure 56. serial peripheral interface block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 6 figure 57. single master/ single slave application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 figure 58. generic ss timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 figure 59. hardware/software slave select management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 figure 60. data clock timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 figure 61. clearing the wcol bit (wri te collision flag) so ftware sequence . . . . . . . . . . . . . . . . . . . . 123 figure 62. single master / multiple slave configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 figure 63. sci block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 figure 64. word length programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 figure 65. sci baud rate and extended prescaler block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 figure 66. bit sampling in reception mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 figure 67. i2c bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 figure 68. i2c interface block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 figure 69. transfer sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 figure 70. event flags and interrupt generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 figure 71. i2c3s interface block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 figure 72. i2c bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 figure 73. 16-bit word write operation flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 figure 74. 16-bit word read operation flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 figure 75. transfer sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 figure 76. byte write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 figure 77. page write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 figure 78. current address read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 figure 79. random read (dummy write + restart + current address read). . . . . . . . . . . . . . . . . . . . . 175 figure 80. random read (dummy write + stop + start + current address read) . . . . . . . . . . . . . . . . . 176 figure 81. sequential read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 figure 82. combined format for read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 figure 83. event flags and interrupt generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 figure 84. adc block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 figure 85. pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 figure 86. pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 figure 87. f cpu maximum operating frequency versus v dd supply voltage . . . . . . . . . . . . . . . . . . . 202 figure 88. typical rc frequency vs. rccr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 04 figure 89. typical i dd in run vs. f cpu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 figure 90. typical i dd in run at f cpu = 8 mhz. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 figure 91. typical i dd in slow vs. f cpu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 figure 92. typical i dd in wait vs. f cpu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 figure 93. typical i dd in wait at f cpu = 8 mhz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 figure 94. typical i dd in slow-wait vs. f cpu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 figure 95. typical i dd vs. temp. at v dd = 5 v and f cpu = 8 mhz . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 figure 96. typical application with an external clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 figure 97. typical application with a crystal or ceramic resonator . . . . . . . . . . . . . . . . . . . . . . . . . . 211 figure 98. two typical applications with unused i/o pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 figure 99. typical v ol at v dd = 2.4 v (std i/os) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
list of figures st72344xx st72345xx 14/247 doc id 12321 rev 5 figure 100. typical v ol at v dd = 3 v (std i/os) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 figure 101. typical v ol at v dd = 5 v (std i/os) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 figure 102. typical v ol at v dd = 2.4 v (high-sink i/os) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 figure 103. typical v ol at v dd = 3 v (high-sink i/os). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 figure 104. typical v ol at v dd = 5 v (high-sink i/os) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 figure 105. typical v ol vs. v dd (std i/os, 2 ma) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 figure 106. typical v ol vs. v dd (std i/os, 6 ma) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 figure 107. typical v ol vs. v dd (hs i/os, i io = 8 ma) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 figure 108. typical v ol vs. v dd (hs i/os, i io = 2 ma) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 figure 109. typical v ol vs. v dd (hs i/os, i io = 12 ma) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 figure 110. typical v dd ? v oh at v dd = 2.4 v (std i/os) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 figure 111. typical v dd ? v oh at v dd = 3 v (std i/os) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 figure 112. typical v dd ? v oh at v dd = 4 v (std) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 figure 113. typical v dd ? v oh at v dd = 5 v (std) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 figure 114. typical v dd ? v oh vs. vdd (high sink) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 figure 115. reset pin protection when lvd is enabled(1)(2)(3)(4). . . . . . . . . . . . . . . . . . . . . . . . . . 223 figure 116. reset pin protection when lvd is disabled(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 figure 117. adc accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 figure 118. typical a/d converter application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226 figure 119. 32-pin low profile quad flat package (7 x 7 mm) outline . . . . . . . . . . . . . . . . . . . . . . . . . . 227 figure 120. 40-lead very thin fine pitch quad flat no-lead package outline . . . . . . . . . . . . . . . . . . . . . 228 figure 121. 44-pin low profile quad flat package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 29 figure 122. 48-pin low profile quad flat package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 30 figure 123. st7234x ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236
st72344xx st72345xx introduction doc id 12321 rev 5 15/247 1 introduction the st7234x devices are members of the st7 microcontroller family. ta b l e 2 gives the available part numbers and details on the devices. all devices are based on a common industry-standard 8-bit core, featuring an enhanced instruction set. they feature single-voltage flash memory with byte-by-byte in-circuit programming (icp) and in-application progra mming (iap) capabilities. under software control, all devices can be placed in wait, slow, auto-wakeup from halt, active-halt or halt mode, reducing power cons umption when the applic ation is in idle or stand-by state. the enhanced instruction set and addressing modes of the st7 offer both power and flexibility to software developers, enabling th e design of highly efficient and compact application code. in addition to standard 8-bit data management, all st7 microcontrollers feature true bit manipulation, 8x8 unsigned multiplication and indirect addressing modes. the devices feature an on-chip debug module (dm) to support in-circuit debugging (icd). for a description of the dm registers, refer to the st7 icc protocol reference manual. figure 1. general block diagram 8-bit core alu address and data bus osc1 control program (16 k - 32 kbytes) v dd reset port f pf (6-bits) timer a beep port a ram (512- 1024 bytes) port c 10-bit adc v aref v ssa port b pb (5-bits) pwm art timer b pa (5-bits) port d pd (6-bits) spi pc (8-bits) v ss watchdog clock control lvd osc2 memory mcc/rtc/beep avd i2cmms port e pe (2-bits) sci i2c3sns internal rc
introduction st72344xx st72345xx 16/247 doc id 12321 rev 5 table 2. st72344xx and st72345xx features features st72344k2, st72344k4, st72344s2, st72344s4 st72345c4 program memory - bytes 8k 16k 16k ram (stack) - bytes 512 bytes (256 bytes) 1 kbyte (256 bytes) 1 kbyte (256 bytes) eeprom data - bytes 256 256 256 common peripherals window watchdog, 2 16-bit timers, sci, spi, i2cmms other peripherals 10-bit adc i2c3sns, 10-bit adc cpu frequency 8 mhz @ 3.3 v to 5.5 v, 4 mhz @ 2.7 v to 5.5 v temperature range -40 c to +85 c package lqfp32 7x7, lqfp44 10x10 lqfp48 7x7
st72344xx st72345xx pin description doc id 12321 rev 5 17/247 2 pin description figure 2. lqfp32 package pinout iccdata / miso / pc4 ain14 / mosi / pc5 iccclk / sck / pc6 ain15 / ss / pc7 (hs) pa3 ain13 / ocmp1_b / pc1 icap2_b / (hs) pc2 icap1_b / (hs) pc3 ocmp1_a / ain10 / pf4 icap1_a / (hs) pf6 extclk_a / (hs) pf7 ain12 / ocmp2_b / pc0 v dda v ssa ain8 / pf0 (hs) pf1 iccsel pa7 (hs) / scl pa6 (hs) / sda pa 4 ( h s ) osc1 osc2 v ss _2 reset pb0 pe1 / rdi pe0 / tdo v dd _2 pd1 / ain1 pd0 / ain0 pb4 (hs) pb3 eix associated external interrupt vector (hs) 20ma high sink capability 32 31 30 29 28 27 26 25 24 23 21 20 19 18 17 9 1011 1213141516 1 2 3 4 5 6 7 8 ei1 ei3 ei0 ei2 ei0 22
pin description st72344xx st72345xx 18/247 doc id 12321 rev 5 figure 3. lqfp44 package pinout mco / ain8 / pf0 beep / (hs) (hs) pf2 ocmp1_a / ain10 / pf4 icap1_a / (hs) pf6 extclk_a / (hs) pf7 v dd_0 v ss_0 ain5 / pd5 v dda v ssa 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 12 13 14 15 16 17 18 19 20 21 22 1 2 3 4 5 6 7 8 9 10 11 ei2 ei3 ei0 ei1 pb3 (hs) pb4 ain0 / pd0 ain1 / pd1 ain2 / pd2 ain3 / pd3 ain4 / pd4 rdi / pe1 pb0 pb1 pb2 pc6 / sck / iccclk pc5 / mosi / ain14 pc4 / miso / iccdata pc3 (hs) / icap1_b pc2 (hs) / icap2_b pc1 / ocmp1_b / ain13 pc0 / ocmp2_b / ain12 v ss_1 v dd_1 pa 3 ( h s ) pc7 / ss / ain15 v ss _2 reset iccsel pa7 (hs) / scl pa6 (hs) / sda pa 5 ( h s ) pa 4 ( h s ) pe0 / tdo v dd _2 osc1 osc2 ei0
st72344xx st72345xx pin description doc id 12321 rev 5 19/247 figure 4. lqfp48 package pinout note: for external pin connection guidelines, refer to section 13: electrical characteristics on page 199 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 12 13 14 15 16 17 18 19 20 21 22 1 2 3 4 5 6 7 8 9 10 11 48 47 46 45 reset iccsel pa 7 ( h s ) / s c l pa 6 ( h s ) / s da pa 5 ( h s ) pa 4 ( h s ) pd6/sda3sns v dd_2 osc1 osc2 v ss_2 pb3 (hs) pb4 ain0 / pd0 ain1 / pd1 ain3 / pd3 rdi / pe1 pb0 pb1 pb2 ain2 / pd2 pe0/td0 ain4 / pd4 mco / ain8 / pf0 beep / (hs) pf1 (hs) pf2 ocmp1_a / ain10 / pf4 icap1_a / (hs) pf6 extclk_a / (hs) pf7 v dd_0 v ss_0 ain5 / pd5 v dda v ssa pc6 / sck / iccclk pc5 / mosi / ain14 pc4 / miso / iccdata pc3 (hs) / icap1_b pc2 (hs) / icap2_b pc1 / ocmp1_b / ain13 pc0 / ocmp2_b / ain12 v ss_1 v dd_1 pa 3 ( h s ) pc7 / ss / ain15 nc nc pd7/scl3sns ei2 ei3 ei0 ei1 ei0
pin description st72344xx st72345xx 20/247 doc id 12321 rev 5 legend / abbreviations for ta b l e 3 : type: i = input, o = output, s = supply input level: a = dedicated analog input in/output level: c t = cmos 0.3v dd /0.7v dd with input trigger output level: hs = 20 ma high sink (on n-buffer only) port and control configuration: input: float = floating, wpu = weak pull-up, int = interrupt 1) , ana = analog output: od = open drain 2) , pp = push-pull the reset configuration of each pin is shown in bold. this configuration is valid as long as the device is in reset state. on the chip, each i/o port may have up to 8 pads. pads that are not bonded to external pins are set in input pull-up configuration after reset through the option byte package selection. the configuration of these pads must be kept at reset state to avoid added current consumption. table 3. device pin description pin n pin name type level port main function (after reset) alternate function lqfp32 lqfp44 lqfp48 input output input (1) output float wpu int ana od pp 11314v dda (2) s analog supply voltage 21415v ssa (2) s analog ground voltage 3 15 16 pf0/mco/ain8 i/o c t xei1xxxport f0 main clock out (f osc /2) adc analog input 8 4 16 17 pf1 (hs)/beep i/o c t hs x ei1 x x port f1 beep signal output -1718pf2 (hs) (3) i/o c t hs x ei1 x x port f2 5 18 19 pf4/ocmp1_a/ain10 i/o c t xx xxxport f4 timer a output compare 1 adc analog input 10 6 19 20 pf6 (hs)/icap1_a i/o c t hs x x x x port f6 timer a input capture 1 7 20 21 pf7 (hs)/extclk_a i/o c t hs x x x x port f7 timer a external clock source -2122v dd_0 (2) s digital main supply voltage -2223v ss_0 (2) s digital ground voltage 8 23 24 pc0/ocmp2_b/ain12 i/o c t xx xxxport c0 timer b output compare 2 adc analog input 12 9 24 27 pc1/ocmp1_b/ain13 i/o c t xx xxxport c1 timer b output compare 1 adc analog input 13
st72344xx st72345xx pin description doc id 12321 rev 5 21/247 10 25 28 pc2 (hs)/icap2_b i/o c t hs x x x x port c2 timer b input capture 2 11 26 29 pc3 (hs)/icap1_b i/o c t hs x x x x port c3 timer b input capture 1 12 27 30 pc4/miso/iccdata i/o c t xx xxport c4 spi master in / slave out data icc data input 13 28 31 pc5/mosi/ain14 i/o c t xx xxxport c5 spi master out / slave in data adc analog input 14 14 29 32 pc6/sck/iccclk i/o c t xx xxport c6 spi serial clock icc clock output 15 30 33 pc7/ss /ain15 i/o c t xx xxxport c7 spi slave select (active low) adc analog input 15 16 31 34 pa3 (hs) i/o c t hs x ei0 x x port a3 -3235v dd_1 (2) s digital main supply voltage -3336v ss_1 (2) s digital ground voltage - - 37 pd7 (3) / scl3sns i/o c t hs x t (4) port d7 i2c3sns serial clock - - 38 pd6 (3) / sda3sns i/o c t hs x t port d6 i2c3sns serial data 17 34 39 pa4 (hs) i/o c t hs x x x x port a4 - 35 40 pa5 (hs) (3) i/o c t hs x x x x port a5 18 36 41 pa6 (hs)/sda i/o c t hs x t port a6 i2c serial data 19 37 42 pa7 (hs)/scl i/o c t hs x t port a7 i2c serial clock 20 38 43 iccsel (5) i icc mode selection 21 39 44 reset i/o c t top priority non maskable interrupt. 22 40 45 v ss_2 (2) s digital ground voltage 23 41 46 osc2 o resonator oscillator inverter output 24 42 47 osc1 i external clock input or resonator oscillator inverter input 25 43 48 v dd_2 (2) s digital main supply voltage 26 44 1 pe0/tdo i/o c t x x x x port e0 sci transmit data out table 3. device pin description (continued) pin n pin name type level port main function (after reset) alternate function lqfp32 lqfp44 lqfp48 input output input (1) output float wpu int ana od pp
pin description st72344xx st72345xx 22/247 doc id 12321 rev 5 27 1 2 pe1/rdi i/o c t x ei0 x x port e1 sci receive data in 28 2 3 pb0 i/o c t xei2 xxport b0 - 3 4 pb1 (3) i/o c t xei2 xxport b1 - 4 5 pb2 (3) i/o c t xei2 xxport b2 29 5 6 pb3 i/o c t xei2xxport b3 30 6 7 pb4 (hs) i/o c t hs x ei3 x x port b4 31 7 8 pd0/ain0 i/o c t x x x x x port d0 adc analog input 0 32 8 9 pd1/ain1 i/o c t x x x x x port d1 adc analog input 1 - 9 10 pd2/ain2 i/o c t x x x x x port d2 adc analog input 2 - 10 11 pd3/ain3 i/o c t x x x x x port d3 adc analog input 3 - 11 12 pd4/ain4 i/o c t x x x x x port d4 adc analog input 4 - 12 13 pd5/ain5 i/o c t x x x x x port d5 adc analog input 5 1. in the interrupt input column, ?eix? defines the associated ex ternal interrupt vector. if the weak pull-up column (wpu) is merged with the interrupt column (int), t hen the i/o configuration is pull-up interrupt input, else the configuration is floati ng interrupt input. 2. it is mandatory to connect all available v dd and v dda pins to the supply voltage and all v ss and v ssa pins to ground. 3. pulled-up by hardware when not present on the package. 4. in the open drain output column, ?t? defines a tr ue open drain i/o (p-buffer and protection diode to v dd are not implemented). 5. internal weak pull-down. table 3. device pin description (continued) pin n pin name type level port main function (after reset) alternate function lqfp32 lqfp44 lqfp48 input output input (1) output float wpu int ana od pp
st72344xx st72345xx register and memory map doc id 12321 rev 5 23/247 3 register and memory map as shown in figure 5 , the mcu is capable of addressing 64 kbytes of memories and i/o registers. the available memory locations consist of 128 bytes of register locations, up to 1 kbytes of ram, 256 bytes of data eeprom and up to 16 kbytes of user program memory. the ram space includes up to 256 bytes for the stack from 0100h to 01ffh. the highest address bytes contain the user reset and interrupt vectors. figure 5. memory map 0000h ram program memory interrupt & reset vectors hw registers 0080h 007fh bfffh see table 4 c000h ffdfh ffe0h ffffh short addressing ram (zero page) 256 bytes stack 16-bit addressing ram 0100h 01ffh 047fh 0080h 0200h 00ffh (512 or 1k bytes) 0480h 047fh data eeprom (256 bytes) reserved reserved 0c00h 0cffh 0bffh 0d00h see table 17 ffffh e000h c000h (8 or 16 kbytes) 16 kbytes 8 kbytes sector 2 sector 1 ffffh e000h c000h sector 0 f000h (4k) or fc00h (1k) or fe00h (0.5k) or fb00h (2k)
register and memory map st72344xx st72345xx 24/247 doc id 12321 rev 5 table 4. hardware register map address block register label register name reset status (1) remarks (2) 0000h 0001h 0002h port a (3) pa d r paddr pao r port a data register port a data direction register port a option register 00h (4) 00h 00h r/w r/w r/w 0003h 0004h 0005h port b (3) pbdr pbddr pbor port b data register port b data direction register port b option register 00h (4) 00h 00h r/w r/w r/w 0006h 0007h 0008h port c (3) pcdr pcddr pcor port c data register port c data direction register port c option register 00h (4) 00h 00h r/w r/w r/w 0009h 000ah 000bh port d (3) pdadr pdddr pdor port d data register port d data direction register port d option register 00h (4) 00h 00h r/w r/w r/w 000ch 000dh 000eh port e (3) pedr peddr peor port e data register port e data direction register port e option register 00h (4) 00h 00h r/w r/w r/w 000fh 0010h 0011h port f (3) pfdr pfddr pfor port f data register port f data direction register port f option register 00h (4) 00h 00h r/w r/w r/w 0012h to 0016h reserved area (5 bytes) 0017h 0018h rc rccrh rccrl rc oscillator control register high rc oscillator control register low ffh 03h r/w r/w 0019h reserved area (1 byte) 001ah to 001fh dm (5) reserved area (6 bytes) 00020h eeprom eecsr data eeprom co ntrol/status register 00h r/w 0021h 0022h 0023h spi spidr spicr spicsr spi data i/o register spi control register spi control status register xxh 0xh 00h r/w r/w r/w 0024h 0025h 0026h 0027h itc ispr0 ispr1 ispr2 ispr3 interrupt software priority register 0 interrupt software priority register 1 interrupt software priority register 2 interrupt software priority register 3 ffh ffh ffh ffh r/w r/w r/w r/w 0028h eicr external interrupt control register 00h r/w 00029h flash fcsr flash control/status register 00h r/w 002ah wwdg wdgcr watchdog control register 7fh r/w 002bh si sicsr system integrity control/status register 000x 000xb r/w 002ch 002dh mcc mccsr mccbcr main clock control/status register mcc beep control register 00h 00h r/w r/w 002eh 002fh awu awucsr awupr awu control/status register awu prescaler register 00h ffh r/w r/w 0030h wwdg wdgwr window watchdog control register 7fh r/w
st72344xx st72345xx register and memory map doc id 12321 rev 5 25/247 0031h 0032h 0033h 0034h 0035h 0036h 0037h 0038h 0039h 003ah 003bh 003ch 003dh 003eh 003fh timer a tacr2 tacr1 tac s r ta i c 1 h r taic1lr tao c 1 h r tao c 1 l r tachr tac l r taachr ta ac l r ta i c 2 h r taic2lr tao c 2 h r tao c 2 l r timer a control register 2 timer a control register 1 timer a control/status register timer a input capture 1 high register timer a input capture 1 low register timer a output compare 1 high register timer a output compare 1 low register timer a counter high register timer a counter low register timer a alternate counter high register timer a alternate counter low register timer a input capture 2 high register timer a input capture 2 low register timer a output compare 2 high register timer a output compare 2 low register 00h 00h xxh xxh xxh 80h 00h ffh fch ffh fch xxh xxh 80h 00h r/w r/w r/w read only read only r/w r/w read only read only read only read only read only read only r/w r/w 0040h reserved area (1 byte) 0041h 0042h 0043h 0044h 0045h 0046h 0047h 0048h 0049h 004ah 004bh 004ch 004dh 004eh 004fh timer b tbcr2 tbcr1 tbcsr tbic1hr tbic1lr tboc1hr tboc1lr tbchr tbclr tbachr tbaclr tbic2hr tbic2lr tboc2hr tboc2lr timer b control register 2 timer b control register 1 timer b control/status register timer b input capture 1 high register timer b input capture 1 low register timer b output compare 1 high register timer b output compare 1 low register timer b counter high register timer b counter low register timer b alternate counter high register timer b alternate counter low register timer b input capture 2 high register timer b input capture 2 low register timer b output compare 2 high register timer b output compare 2 low register 00h 00h xxh xxh xxh 80h 00h ffh fch ffh fch xxh xxh 80h 00h r/w r/w r/w read only read only r/w r/w read only read only read only read only read only read only r/w r/w 0050h 0051h 0052h 0053h 0054h 0055h 0056h 0057h sci scisr scidr scibrr scicr1 scicr2 scierpr scietpr sci status register sci data register sci baud rate register sci control register 1 sci control register 2 reserved area sci extended receive prescaler register sci extended transmit prescaler register c0h xxh 00h x000 0000b 00h -- 00h 00h read only r/w r/w r/w r/w r/w r/w 0058h 0059h 005ah 005bh 005ch 005dh 005eh i 2 c i2ccr i2csr1 i2csr2 i2cccr i2coar1 i2coar2 i2cdr i 2 c control register i 2 c status register 1 i 2 c status register 2 i 2 c clock control register i 2 c own address register 1 i 2 c own address register2 i 2 c data register 00h 00h 00h 00h 00h 40h 00h r/w read only read only r/w r/w r/w r/w 005fh reserved area (1 byte) table 4. hardware register map (continued) address block register label register name reset status (1) remarks (2)
register and memory map st72344xx st72345xx 26/247 doc id 12321 rev 5 0060h 0061h 0062h 0063h 0064h 0065h 0066h 0067h 0068h 0069h i 2 c3sns i2c3scr1 i2c3scr2 i2c3ssr i2c3sbcr i2c3ssar1 i2c3scar1 i2c3ssar2 i2c3scar2 i2c3ssar3 i2c3scar3 i 2 c3sns control register 1 i 2 c3sns control register 2 i 2 c3sns status register i 2 c3sns byte count register i 2 c3sns slave address 1 register i 2 c3sns current address 1 register i 2 c3sns slave address 2 register i 2 c3sns current address 2 register i 2 c3sns slave address 3 register i 2 c3sns current address 3 register 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h r/w r/w read only read only r/w r/w r/w r/w r/w r/w 0070h 0071h 0072h adc adccsr adcdrh adcdrl a/d control status register a/d data register high a/d data low register 00h xxh 0000 00xxb r/w read only read only 0073h to 007fh reserved area (13 bytes) 1. x = undefined. 2. r/w = read/write. 3. the bits associated with unavailable pi ns must always keep their reset value. 4. the contents of the i/o port dr registers are readable only in out put configuration. in input c onfiguration, the values of th e i/o pins are returned instead of the dr register contents. 5. for a description of the debug module regist ers, see st7 icc protocol reference manual. table 4. hardware register map (continued) address block register label register name reset status (1) remarks (2)
st72344xx st72345xx flash program memory doc id 12321 rev 5 27/247 4 flash program memory 4.1 introduction the st7 single voltage extended flash (xflash) is a non-volatile memory that can be electrically erased and programmed either on a byte-by-byte basis or up to 32 bytes in parallel. the xflash devices can be programmed off-board (plugged in a programming tool) or on- board using in-circuit programming or in-application programming. the array matrix organization allows each sector to be erased and reprogrammed without affecting other sectors. 4.2 main features icp (in-circuit programming) iap (in-application programming) ict (in-circuit testing) for downloading and executing user application test patterns in ram sector 0 size configurable by option byte read-out and write protection 4.3 programming modes the st7 can be programmed in three different ways: insertion in a programming tool. in this mode, flash sectors 0 and 1, option byte row and data eeprom (if present) c an be programmed or erased. in-circuit programming. in this mode, flash sectors 0 and 1, option byte row and data eeprom (if present) can be pr ogrammed or erased without removing the device from the application board. in-application programm ing. in this mode, sector 1 a nd data eeprom (if present) can be programmed or erased without removing the device from the application board and while the application is running.
flash program memory st72344xx st72345xx 28/247 doc id 12321 rev 5 4.3.1 in-circuit programming (icp) icp uses a protocol called icc (in-circuit communication) which allows an st7 plugged on a printed circuit board (pcb) to communicate with an external programming device connected via cable. icp is performed in three steps: switch the st7 to icc mode (in-circuit communic ations). this is done by driving a specific signal sequence on the iccclk/data pins while the reset pin is pulled low. when the st7 enters icc mode, it fetches a specific reset vector which points to the st7 system memory containing the icc protocol routine. this routine enables the st7 to receive bytes from the icc interface. download icp driver code in ram from the iccdata pin execute icp driver code in ram to program the flash memory depending on the icp driver code downloaded in ram, flash memory programming can be fully customized (number of bytes to program, program locations, or selection of the serial communication interface for downloading). 4.3.2 in-applicati on programming (iap) this mode uses an iap driver program previously programmed in sector 0 by the user (in icp mode). this mode is fully controlled by user software. this allows it to be adapted to the user application, (user-defined strategy for entering programming mode, choice of communications protocol used to fetch the data to be stored etc.) iap mode can be used to program any memory areas except sector 0, which is write/erase protected to allow recovery in case errors occur during the programming operation. 4.4 icc interface icp needs a minimum of 4 and up to 7 pins to be connected to the programming tool. these pins are: reset : device reset v ss : device power supply ground iccclk: icc output serial clock pin iccdata: icc input serial data pin iccsel: icc selection osc1: main clock input for external source (not required on devices without osc1/osc2 pins) v dd : application board power supply (optional, see note 3) note: 1 if the iccclk or iccdata pins are only used as outputs in the application, no signal isolation is necessary. as soon as the programmin g tool is plugged to the board, even if an icc session is not in progress, the iccclk and iccdata pins are not available for the application. if they are used as inputs by the application, isolation such as a serial resistor has to be implemented in case another device forces the signal. refer to the programming tool documentation for recommended resistor values. 2 during the icp session, the programming tool must control the reset pin. this can lead to conflicts between the programming tool and the application reset circuit if it drives more than 5 ma at high level (push pull output or pull-up resistor<1k). a schottky diode can be used to
st72344xx st72345xx flash program memory doc id 12321 rev 5 29/247 isolate the application reset circuit in this case. when using a classical rc network with r>1k or a reset management ic with open drain output and pull-up resistor>1k, no additional components are needed. in all cases the user must ensure that no external reset is generated by the application during the icc session. 3 the use of pin 7 of the icc connector depends on the programming tool architecture. this pin must be connected when using most st programming tools (it is used to monitor the application power supply). please refer to the programming tool manual. 4 pin 9 has to be connected to the osc1 pin of the st7 when the clock is not available in the application or if the selected clock option is not programmed in the option byte. st7 devices with multi-oscillator capab ility need to have osc2 grounded in this case. 5 in ?enabled option byte? mode (38-pulse icc mode), th e internal rc oscillator is forced as a clock source, regardless of the selection in the option byte. caution: during normal operation the iccclk pin must be internally or externally pulled- up (external pull-up of 10 k mandatory in noisy environment) to avoid entering icc mode unexpectedly during a reset. in the application, even if the pin is configured as output, any reset will put it back in input pull-up. figure 6. typical icc interface 4.5 memory protection there are two different types of memory protection: read out protection and write/erase protection which can be applied individually. 4.5.1 readout protection readout protection, when selected provides a protection against program memory content extraction and against write access to flash memory. even if no protection can be considered as totally unbreakable, the feature provides a very high level of protection for a general purpose microcontroller. both program and data e 2 memory are protected. icc connector iccdata iccclk reset vdd he10 connector type application power supply 1 2 4 6 8 10 97 5 3 programming tool icc connector application board icc cable (see note 3) 10k vss iccsel st7 c l2 c l1 osc1 osc2 optional see note 1 see note 2 application reset source application i/o (see note 4)
flash program memory st72344xx st72345xx 30/247 doc id 12321 rev 5 in flash devices, this protection is removed by reprogramming the option. in this case, both program and data e 2 memory are automatically erased, and the device can be reprogrammed. read-out protection selection depends on the device type: in flash devices it is enabled and removed through the fmp_r bit in the option byte. in rom devices it is enabled by mask option specified in the option list. 4.5.2 flash write/erase protection write/erase protection, when set, makes it impossible to both overwrite and erase program memory. it does not apply to e 2 data. its purpose is to provide advanced security to applications and prevent any change being made to the memory content. warning: once set, write/erase protection can never be removed. a write-protected flash device is no longer reprogrammable. write/erase protection is enabled through the fmp_w bit in the option byte. 4.6 register description 4.6.1 flash control/st atus register (fcsr) reset value: 0000 0000 (00h) 1st rass key: 0101 0110 (56h) 2nd rass key: 1010 1110 (aeh) note: this register is reserved for programming using icp, iap or other programming methods. it controls the xflash programming and erasing operations. for details on xflash programming, refer to the st7 flash programming reference manual. when an epb or another programm ing tool is used (in socket or icp mode), the rass keys are sent automatically. 7 0 00000optlatpgm read/write
st72344xx st72345xx data eeprom doc id 12321 rev 5 31/247 5 data eeprom 5.1 introduction the electrically erasable programmable read only memory can be used as a non-volatile backup for storing data. usin g the eeprom requires a basic access protocol described in this chapter. 5.2 main features up to 32 bytes programmed in the same cycle eeprom mono-voltag e (charge pump) chained erase and programming cycles internal control of the global programming cycle duration wait mode management readout protection figure 7. eeprom block diagram 5.3 memory access the data eeprom memory read/write access modes are controlled by the e2lat bit of the eeprom control/status register (eecsr). the flowchart in figure 8 describes these different memory access modes. eecsr high voltage pump 0 e2lat 0 0 0 0 0 e2pgm eeprom memory matrix (1 row = 32 x 8 bits) address decoder data multiplexer 32 x 8 bits data latches row decoder data bus 4 4 4 128 128 address bus
data eeprom st72344xx st72345xx 32/247 doc id 12321 rev 5 read operation (e2lat = 0) the eeprom can be read as a normal rom lo cation when the e2lat bit of the eecsr register is cleared. on this device, data eeprom can also be used to execute machine code . take care not to write to the data eeprom while executing from it. this would result in an unexpected code being executed. write operation (e2lat = 1) to access the write mode, the e2lat bit has to be set by software (the e2pgm bit remains cleared). when a write access to the eeprom ar ea occurs, the value is latched inside the 32 data latches according to its address. when e2pgm bit is set by the software, all the previous bytes written in the data latches (up to 32) are programmed in the eeprom cells . the effective high address (row) is determined by the last eeprom write sequence. to avoid wr ong programming, the user must take care that all the bytes written between two programming sequences have the same high address: only the five least si gnificant bits of the address can change. the programming cycle is fully completed when the e2pgm bit is cleared. note: care should be taken during the programming cycle. writing to the same memory location will over-program the memory (logical and between the two write access data result) because the data latches are only cleared at the end of the programming cycle and by the falling edge of the e2lat bit. it is not possible to read the latched data. this note is illustrated by the figure 10 . figure 8. data eeprom programming flowchart read mode e2lat = 0 e2pgm = 0 write mode e2lat = 1 e2pgm = 0 read bytes in eeprom area write up to 32 bytes in eeprom area (with the same 11 msb of the address) start programming cycle e2lat=1 e2pgm=1 (set by software) e2pgm 01 cleared by hardware
st72344xx st72345xx data eeprom doc id 12321 rev 5 33/247 figure 9. data eeprom write operation note: if a programming cycle is interrupted (by reset action), the integrity of the data in memory will not be guaranteed. 5.4 power saving modes 5.4.1 wait mode the data eeprom can ent er wait mode on execution of the wfi instruction of the microcontroller or when the microc ontroller enters ac tive halt mode.the data eeprom will immediately enter this mode if there is no programming in progress, otherwise the data eeprom will finish the cycle an d then enter wait mode. 5.4.2 active-halt mode refer to wait mode. 5.4.3 halt mode the data eeprom immediately ent ers halt mode if the microcon troller execut es the halt instruction. therefore the eeprom will stop the function in progress, and data may be corrupted. 5.5 access error handling if a read access o ccurs while e2lat = 1, then th e data bus will not be driven. if a write access occurs while e2lat = 0, then the data on the bus will not be latched. if a programming cycle is interrupted (by reset action), the integrity of the data in memory will not be guaranteed. byte 1 byte 2 byte 32 phase 1 programming cycle read operation impossible phase 2 read operation possible e2lat bit e2pgm bit writing data latches waiting e2pgm and e2lat to fall set by user application cleared by hardware ? row / byte ? 0 1 2 3 ... 30 31 physical address 0 00h...1fh 1 20h...3fh ... n nx20h...nx20h+1fh row definition
data eeprom st72344xx st72345xx 34/247 doc id 12321 rev 5 5.6 data eeprom readout protection the readout protection is enabled through an option bit (see option byte section). when this option is selected, the programs and data stored in the eeprom memory are protected against read-out (including a rewrite protection). in flash devices, when this protection is removed by reprogramming the option byte, the entire program memory and eeprom is first automatically erased. note: both program memory and data eeprom are protected using the same option bit. figure 10. data eeprom programming cycle e2lat erase cycle write cycle e2pgm t prog read operation not possible write of data read operation possible internal programming voltage latches i bit in cc register all interrupts must be masked 1) note 1: refer to programming of eeprom data on page 244
st72344xx st72345xx data eeprom doc id 12321 rev 5 35/247 5.7 register description 5.7.1 eeprom control/st atus register (eecsr) reset value: 0000 0000 (00h) bits 7:2 = reserved, forced by hardware to 0. bit 1 = e2lat latch access transfer this bit is set by software. it is cleared by hardware at the end of the programming cycle. it can only be cleared by software if the e2pgm bit is cleared. 0: read mode 1: write mode bit 0 = e2pgm programming control and status this bit is set by software to begin the programming cycle. at the end of the programming cycle, this bit is cleared by hardware. 0: programming finished or not yet started 1: programming cycle is in progress note: if the e2pgm bit is cleared during the programming cycle, the memory data is not guaranteed 7 0 000000e2late2pgm read/write table 5. data eeprom register map and reset values address (hex.) register label 76543210 0020h eecsr reset value000000 e2lat 0 e2pgm 0
central processing unit st72344xx st72345xx 36/247 doc id 12321 rev 5 6 central processing unit 6.1 introduction this cpu has a full 8-bit architecture and contains six internal registers allowing efficient 8- bit data manipulation. 6.2 main features enable executing 63 basic instructions fast 8-bit by 8-bit multiply 17 main addressing modes (with indirect addressing mode) two 8-bit index registers 16-bit stack pointer low power halt and wait modes priority maskable hardware interrupts non-maskable software/hardware interrupts 6.3 cpu registers the six cpu registers shown in figure 11 are not present in the memory mapping and are accessed by specific instructions. accumulator (a) the accumulator is an 8-bit general purpose register used to hold operands and the results of the arithmetic and logic calculations and to manipulate data. index registers (x and y) these 8-bit registers are used to create effective addresses or as temporary storage areas for data manipulation. (the cross-assembler generates a precede instruction (pre) to indicate that the following instruction refers to the y register.) the y register is not affected by the interrupt automatic procedures. program counter (pc) the program counter is a 16-bit register containing the address of the next instruction to be executed by the cpu. it is made of two 8-bit registers pcl (program counter low which is the lsb) and pch (program counter high which is the msb).
st72344xx st72345xx central processing unit doc id 12321 rev 5 37/247 figure 11. cpu registers 6.3.1 condition code register (cc) reset value: 111x1xxx the 8-bit condition code register contains the interrupt masks and four flags representative of the result of the instruction just executed. this register can also be handled by the push and pop instructions. these bits can be individually tested and/or controlled by specific instructions. arithmetic management bits bit 4 = h half carry . this bit is set by hardware when a carry occurs between bits 3 and 4 of the alu during an add or adc instructions. it is reset by hardware during the same instructions. 0: no half carry has occurred. 1: a half carry has occurred. this bit is tested using the jrh or jrnh instruction. the h bit is useful in bcd arithmetic subroutines. accumulator x index register y index register stack pointer condition code register program counter 70 1c 1i1hi0nz reset value = reset vector @ fffeh-ffffh 70 70 70 0 7 15 8 pch pcl 15 8 70 reset value = stack higher address reset value = 1x 11x1xx reset value = xxh reset value = xxh reset value = xxh x = undefined value 7 0 11i1hi0nzc read/write
central processing unit st72344xx st72345xx 38/247 doc id 12321 rev 5 bit 2 = n negative . this bit is set and cleared by hardware. it is representative of the result sign of the last arithmetic, logical or data manipulation. it?s a copy of the result 7 th bit. 0: the result of the last operation is positive or null. 1: the result of the last operation is negative (that is, the most significant bit is a logic 1). this bit is accessed by the jrmi and jrpl instructions. bit 1 = z zero . this bit is set and cleared by hardware. this bit indicates that the result of the last arithmetic, logical or data manipulation is zero. 0: the result of the last operation is different from zero. 1: the result of the last operation is zero. this bit is accessed by the jreq and jrne test instructions. bit 0 = c carry/borrow. this bit is set and cleared by hardware and software. it indicates an overflow or an underflow has occurred during the last arithmetic operation. 0: no overflow or underflow has occurred. 1: an overflow or underflow has occurred. this bit is driven by the scf and rcf instructions and tested by the jrc and jrnc instructions. it is also affected by the ?bit test and branch?, shift and rotate instructions. interrupt management bits bits 5,3 = i1, i0 interrupt the combination of the i1 and i0 bits gives the current interrupt software priority. these two bits are set/cleared by hardware when entering in interrupt. the loaded value is given by the corresponding bits in the interrupt software priority registers (ixspr). they can be also set/cleared by software with the rim, sim, iret, halt, wfi and push/pop instructions. see the interrupt management chapter for more details. table 6. interrupt software priority priority i1 i0 level 0 (main) 1 0 level 1 0 1 level 2 0 0 level 3 (= interrupt disable) 1 1
st72344xx st72345xx central processing unit doc id 12321 rev 5 39/247 6.3.2 stack pointer (sp) reset value: 01 ffh the stack pointer is a 16-bit register which is always pointing to the next free location in the stack. it is then decremented after data has been pushed onto the stack and incremented before data is popped from the stack (see figure 12 ). since the stack is 256 bytes deep, the 8 most significant bits are forced by hardware. following an mcu reset, or after a reset stack pointer instruction (rsp), the stack pointer contains its reset value (the sp7 to sp0 bits are set) which is the stack higher address. the least significant byte of the stack pointer (called s) can be directly accessed by a ld instruction. note: when the lower limit is exceeded, the stack pointer wraps around to the stack upper limit, without indicating the stack overflow. the previously stored information is then overwritten and therefore lost. the stack also wraps in case of an underflow. the stack is used to save the return address during a subroutine call and the cpu context during an interrupt. the user may also directly manipulate the stack by means of the push and pop instructions. in the case of an interrupt, the pcl is stored at the first location pointed to by the sp. then the other registers are stored in the next locations as shown in figure 12 . when an interrupt is received, the sp is decremented and the context is pushed on the stack. on return from interrupt, the sp is incremented and the context is popped from the stack. a subroutine call occupies two locations and an interrupt five locations in the stack area. 15 8 00000001 read/write 7 0 sp7 sp6 sp5 sp4 sp3 sp2 sp1 sp0 read/write
central processing unit st72344xx st72345xx 40/247 doc id 12321 rev 5 figure 12. stack manipulation example pch pcl sp pch pcl sp pcl pch x a cc pch pcl sp pcl pch x a cc pch pcl sp pcl pch x a cc pch pcl sp sp y call subroutine interrupt event push y pop y iret ret or rsp @ 01ffh @ 0100h stack higher address = 01ffh stack lower address = 0100h
st72344xx st72345xx supply, reset and clock management doc id 12321 rev 5 41/247 7 supply, reset and clock management the device includes a range of utility featur es for securing the application in critical situations (for example in case of a power brown-out), and reducing the number of external components. 7.1 main features clock management ? 1 mhz high-accuracy internal rc o scillator (enabled by option byte) ? 1 to 16 mhz external crystal/cerami c resonator (enabled by option byte) ? external clock input (enabled by option byte) ? pll for multiplying the frequency by 8 or 4 (enabled by option byte) reset sequence manager (rsm) system integrity management (si) ? main supply low voltage detection (lvd) with reset generation (enabled by option byte) ? auxiliary voltage detector (avd) with interr upt capability for mo nitoring the main supply (enabled by option byte) figure 13. clock, reset and supply block diagram cr9 cr8 cr7 cr6 cr5 cr4 cr3 cr2 cr1 cr0 rccrh/rccrl register tunable rc oscillator /2 divider osc 1-16 mhz osc option bit /2 divider pll 1 mhz --> 8 mhz pll 1 mhz --> 4 mhz external clock (0.5-8 mhz) rc clock (1 mhz) pll clock 8/4 mhz osc, plloff oscrange[2:0] option bits crystal osc (0.5-8 mhz) pllx4x8 osc1 osc2 f osc2 main clock controller with real-time clock(mcc/rtc) f cpu 8 mhz 4 mhz 1 mhz option bit /2 divider* div2en option bit* *not available if pllx4 is enabled
supply, reset and clock management st72344xx st72345xx 42/247 doc id 12321 rev 5 7.2 phase locked loop the pll can be used to multiply a 1 mhz frequ ency from the rc oscilla tor or the external clock by 4 or 8 to obtain f osc of 4 or 8 mhz. the pll is enabled and the multiplication factor of 4 or 8 is selected by 3 option bits. refer to ta b l e 7 for the pll configuration depending on the required frequency and the application voltage. refer to section 15.1 for the option byte description. figure 14. pll output frequency timing diagram when the pll is started, after reset or wakeup from halt mode or awufh mode, it outputs the clock after a delay of t startup . when the pll output signal reaches the operating frequency, the locked bit in the sicscr register is set. full pll accuracy (acc pll ) is reached after a stabilization time of t stab (see figure 14 ). refer to section 7.6.5 on page 51 for a description of the locked bit in the sicsr register. caution: the pll is not recommended for applications where timing accuracy is required. caution: when the rc oscillator and the pll are enabled, it is recommended to calibrate this clock through the rccrh and rccrl registers. table 7. pll configurations target ratio v dd pll ratio div2 x4 (1) 1. for a target ratio of x4 between 3.3 v - 3. 65 v, this is the recommended configuration. 2.7 v - 3.65 v x4 off x4 3.3 v - 5.5 v x8 on x8 x8 off 4/8 x freq. locked bit set t stab t lock input output freq. t startup t
st72344xx st72345xx supply, reset and clock management doc id 12321 rev 5 43/247 7.3 multioscillator (mo) the main clock of the st7 can be generated by three different source types coming from the multioscillator block: an external source 4 crystal or ceramic resonator oscillators an internal high-accuracy rc oscillator each oscillator is optimized fo r a given frequency range in terms of consumption and is selectable through the option byte. the associated hardware configurations are shown in ta bl e 8 . refer to the electrical characteristics section for more details. caution: the osc1 and/or osc2 pins must not be left unconnected. for the purposes of failure mode and effect analysis, it should be noted that if the osc1 and/or osc2 pins are left unconnected, the st7 main oscillator may start a nd, in this configuration, could generate an f osc clock frequency in excess of the allowed maximum (>16 mhz.), putting the st7 in an unsafe/undefined state. the product behavior must therefore be considered undefined when the osc pins are left unconnected. 7.3.1 external clock source in this external clock mode, a clock signal (s quare, sinus or triangle) with ~50% duty cycle has to drive the osc1 pin while the osc2 pin is tied to ground. 7.3.2 crystal/cer amic oscillators this family of oscillators has the advantage of prod ucing a very accurate rate on the main clock of the st7. the selection within a list of 4 oscillators with diff erent frequency ranges has to be done by option byte in order to reduce consumption (refer to section 15.1 on page 232 for more details on the frequency ranges). in this mode of the multi-oscillator, the resonator and the load capacitors have to be placed as clos e as possible to the oscillator pins in order to minimize output distorti on and startup stabilizat ion time. the loading capacitance values must be adjusted according to the selected oscillator. these oscillators are not stopped during the rese t phase to avoid losing time in the oscillator startup phase.
supply, reset and clock management st72344xx st72345xx 44/247 doc id 12321 rev 5 table 8. st7 clock sources hardware configuration external clock crystal/ceramic resonators internal rc oscillator osc1 osc2 external st7 source osc1 osc2 load capacitors st7 c l2 c l1 osc1 osc2 st7
st72344xx st72345xx supply, reset and clock management doc id 12321 rev 5 45/247 7.3.3 internal rc oscillator the device contains a high-preci sion internal rc oscillator. it must be calibrated to obtain the frequency required in the application. this is done by software writing a calibration value in the rccrh and rccrl registers. whenever the microcontroller is reset, the rccr return s to its default value (ff 03h), i.e. each time the device is reset, the calibra tion value must be loaded in the rccrh and rccrl registers. predefined calibration values are stored in xflash for 3 and 5v v dd supply voltages at 25 c, as shown in the following table: note: to improve clock stability, it is recommended to place a decoupling capaci tor between the v dd and v ss pins. these two 10-bit values are systematically programmed by st. rccr0 and rccr1 calibration values will be eras ed if the read-out pr otection bit is reset after it has been set. see memory protection on page 29 . caution: if the voltage or temperature conditions change in the application, the frequency may need to be recalibrated. refer to application note an1324 for information on how to calibrate the rc frequency using an external reference signal. 7.4 register description 7.4.1 rc control register (rccrh) reset value: 1111 1111 (ffh) bits 7:0 = cr[9:2] rc oscillator frequency adjustment bits table 9. calibration values rccr conditions address rccr0 v dd = 5 v t a = 25 c f rc = 1 mhz bee0, bee1 rccr1 v dd = 3 v t a = 25 c f rc = 1 mhz bee4, bee5 7 0 cr9 cr8 cr7 cr6 cr5 cr4 cr3 cr2 read/write
supply, reset and clock management st72344xx st72345xx 46/247 doc id 12321 rev 5 7.4.2 rc control register (rccrl) reset value: 0000 0011 (03h) bits 7:2 = reserved, must be kept cleared. bits 1:0 = cr[1:0] rc oscillator frequen cy adjustment bits this 10-bit value must be written immediat ely after reset to adjust the rc oscillator frequency in order to obtain the specified accuracy. the application can store the correct value for each voltage range in eeprom an d write it to this register at startup. 0000h = maximum available frequency 03ffh = lowest available frequency note: to tune the oscillator, write a series of different values in the register un til the correct frequency is reached. the fastest method is to use a dichotomy starting with 200h. 7.5 reset sequence manager (rsm) 7.5.1 introduction the reset sequence manager includes three reset sources as shown in figure 16 : external reset source pulse internal lvd reset (low voltage detection) internal watchdog reset note: a reset can also be triggered following the detection of an illegal op code or prebyte code. refer to section 12.2.1: illegal opcode reset on page 196 for further details. these sources act on the reset pin and it is always kept low during the delay phase. the reset service routine vector is fixed at addresses fffeh-ffffh in the st7 memory map. the basic reset sequence consists of 3 phases as shown in figure 15 : active phase depending on the reset source 256 or 4096 cpu clock cycle delay (selected by option byte) reset vector fetch caution: when the st7 is unprogrammed or fully erased, the flash is blank and the reset vector is not programmed. for this reason, it is recommended to keep the reset pin in low state until programming mode is entered, in order to avoid unwanted behavior. the 256 or 4096 cpu clock cycle delay allows the oscillator to stab ilise and ensures that recovery has taken place from the reset stat e. the shorter or longer clock cycle delay should be selected by option byte to correspond to the stabilization time of the external oscillator used in the application (see section 15.1 on page 232 ). the reset vector fetch phase duration is 2 clock cycles. 7 0 000000cr1cr0 read/write
st72344xx st72345xx supply, reset and clock management doc id 12321 rev 5 47/247 figure 15. reset sequence phases 7.5.2 asynchronous external reset pin the reset pin is both an input and an open-drain output with integrated r on weak pull-up resistor. this pull-up has no fixed value but varies in accordance with the input voltage. it can be pulled low by external circuitry to reset the device. see section 13 on page 199 for more details. a reset signal originating from an external source must have a duration of at least t h(rstl)in in order to be recognized (see figure 17 ). this detection is asynchronous and therefore the mcu can enter reset state even in halt mode. figure 16. reset block diagram 1. see ?illegal opcode reset? on page 198.for mo re details on illegal opcode reset conditions. the reset pin is an asynchronous sign al which plays a major role in ems performance. in a noisy environment, it is recommended to follow the guidelines mentioned in the electrical characteristics section. if the external reset pulse is shorter than t w(rstl)out (see short ext. reset in figure 17 ), the signal on the reset pin may be stretched. otherwise the delay will not be applied (see long ext. reset in figure 17 ). starting from the external reset pulse recognition, the device reset pin acts as an output that is pulled low during at least t w(rstl)out . 7.5.3 external power-on reset if the lvd is disabled by option byte, to start up the microcontroller correctly, the user must ensure by means of an external reset circuit that the reset signal is held low until v dd is over the minimum level specif ied for the selected f osc frequency (see operating conditions on page 202 ). a proper reset signal for a slow rising v dd supply can generally be provided by an external rc network connected to the reset pin. reset active phase internal reset 256 or 4096 clock cycles fetch vector reset r on v dd watchdog reset lvd reset internal reset pulse generator filter illegal opcode reset (1)
supply, reset and clock management st72344xx st72345xx 48/247 doc id 12321 rev 5 7.5.4 internal low-voltage detector (lvd) reset two different reset sequences caused by the internal lvd circuitry can be distinguished: power-on reset voltage-drop reset the device reset pin acts as an output that is pulled low when v dd st72344xx st72345xx supply, reset and clock management doc id 12321 rev 5 49/247 7.6.1 low-voltage detector (lvd) the low-voltage detector function (lvd) generates a static reset when the v dd supply voltage is below a v it- reference value. this means that it secures the power-up as well as the power-down keeping the st7 in reset. the v it- reference value for a voltage drop is lower than the v it+ reference value for power- on in order to avoid a parasitic reset when the mcu starts running and sinks current on the supply (hysteresis). the lvd reset circuitry generates a reset when v dd is below: v it+ when v dd is rising v it- when v dd is falling the lvd function is illustrated in figure 18 . the lvd is an optional function which can be selected by option byte. note: lvd threshold configuration: the voltage threshold can be configured by option byte to be low, medium or high. the configuration should be chosen depending on the f osc and v dd parameters in the application. when correctly configured, the lvd ensures safe power-on and power-off conditions for the microcontroller without using any external components. to determine which lvd thresholds to use: define the minimum operating voltage for the application v app(min) refer to the electrical characteristics sect ion to get the minimum operating voltage for the mcu at the application frequency v dd(min) . select the lvd threshold that ensures that the internal reset is released at v app(min) and activated at v dd(mcumin) during a low-voltage detector reset, the reset pin is held low, thus permitting the mcu to reset other devices. figure 18. low voltage detector vs. reset 7.6.2 auxiliary-voltage detector (avd) the avd is used to provide the application with an early warning of a drop in voltage. if enabled, an interrupt can be generated allowing software to shut down safely before the lvd resets the microcontroller. see figure 19 . note: the avd function is active only if the lvd is enabled through the option byte (see 15.1: option bytes on page 232 ). the activation level of the avd is fixed at around 0.5 mv above the selected lvd threshold. v dd v it+(lvd) reset v it-((lvd) v hys
supply, reset and clock management st72344xx st72345xx 50/247 doc id 12321 rev 5 in the case of a drop in voltage below v it-(avd) , the avdf flag is set and an interrupt request is issued. if v dd rises above the v it+(avd) threshold voltage the avdf bit is cleared automatically by hardware. no interrupt is generated, and therefore software should poll the avdf bit to detect when the voltage has risen, and resume normal processing. figure 19. using the avd to monitor v dd 7.6.3 low-power modes 7.6.4 interrupts the avd interrupt event generates an interrupt if the corresponding avdie bit is set and the interrupt mask in the cc register is reset (rim instruction). v dd v it-(avd) avdf bit 0 reset value if avdie bit = 1 avd interrupt request interrupt process v it-(lvd) lvd reset early warning interrupt (power has dropped, mcu not not yet in reset) 1 0 1 v it+(avd) v hys table 10. low-power mode description mode description wait no effect on si. avd interrupts caus e the device to exit from wait mode. halt the sicsr register is frozen. table 11. interrupt event interrupt event event flag enable control bit exit from wait exit from halt avd event avdf avdie yes no
st72344xx st72345xx supply, reset and clock management doc id 12321 rev 5 51/247 7.6.5 register description system integrity (si) control/status register (sicsr) reset value: 000x 000x (xxh) bit 7 = reserved, must be kept cleared. bit 6 = avdie voltage detector interrupt enable this bit is set and cleared by software. it enables an interrupt to be generated when the avdf flag goes from 0 to 1. the pending interrupt information is automatically cleared when software enters the avd interrupt routine. 0: pdvd interrupt disabled 1: pdvd interrupt enabled bit 5 = avdf voltage detector flag this read-only bit is set and cleared by hardware. if the avdie bit is set, an interrupt request is generated when the avdf bit goes from 0 to 1. refer to figure 19 and to section 7.6.2 for additional details. 0: v dd over v it+(avd) threshold 1: v dd under v it-(avd) threshold bit 4 = lvdrf lvd reset flag this bit indicates that the last reset was generated by the lvd block. it is set by hardware (lvd reset) and cleared by software (writing zero). see wdgrf flag description for more details. when the lvd is disabled by option byte, the lvdrf bit value is undefined. bit 3 = locked pll locked flag this bit is set and cleared by hardware. it is set automatically when the pll reaches its operating frequency. 0: pll not locked 1: pll locked bits 2:1 = reserved, must be kept cleared. bit 0 = wdgrf watchdog reset flag this bit indicates that the last reset was generated by the watchdog peripheral. it is set by hardware (watchdog reset) and cleared by software (writing zero) or an lvd reset (to ensure a stable cleared state of the wdgrf flag when cpu starts). combined with the lvdrf flag information, t he flag description is given by the following table. 7 0 0 pdvdie avdf lvdrf locked 0 0 wdgrf read/write table 12. lvdrf and wdgrf description reset sources lvdrf wdgrf external reset pin 0 0 watchdog 0 1 lv d 1 x
supply, reset and clock management st72344xx st72345xx 52/247 doc id 12321 rev 5 application notes the lvdrf flag is not cleared when another re set type occurs (external or watchdog), the lvdrf flag remains set to keep trace of the original failure. in this case, a watchdog reset can be detected by software while an external reset can not. caution: when the lvd is not activated with the associated option byte, the wdgrf flag can not be used in the application.
st72344xx st72345xx interrupts doc id 12321 rev 5 53/247 8 interrupts 8.1 introduction the st7 enhanced interrupt management provides the following features: hardware interrupts software interrupt (trap) nested or concurrent interrupt management with flexible interrupt priority and level management: ? up to 4 software programmable nesting levels ? up to 16 interrupt vectors fixed by hardware ? 2 non maskable events: reset, trap this interrupt management is based on: bit 5 and bit 3 of the cpu cc register (i1:0), interrupt software priority registers (isprx), fixed interrupt vector addresses located at the high addresses of the memory map (ffe0h to ffffh) sorted by hardware priority order. this enhanced in terrupt controller guarant ees full upward compatib ility with the standard (not nested) st7 interrupt controller. 8.2 masking and processing flow the interrupt masking is managed by the i1 and i0 bits of the cc register and the isprx registers which give the interrupt software priority level of each interrupt vector (see ta bl e 6 ). the processing flow is shown in figure 20 . when an interrupt request has to be serviced: normal processing is suspended at the end of the current instruction execution. the pc, x, a and cc registers are saved onto the stack. i1 and i0 bits of cc register are set according to the corresponding values in the isprx registers of the serviced interrupt vector. the pc is then loaded with the interrupt vector of the interrupt to service and the first instruction of the interrupt service routine is fetched (refer to ?interrupt mapping? table for vector addresses). the interrupt service routine should end with the iret instruction which causes the contents of the saved registers to be recovered from the stack. note: as a consequence of the iret instruction, th e i1 and i0 bits will be restored from the stack and the program in the pr evious level will resume.
interrupts st72344xx st72345xx 54/247 doc id 12321 rev 5 figure 20. interrupt processing flowchart servicing pending interrupts as several interrupts can be pending at the same time, the interrupt to be taken into account is determined by the following two-step process: the highest software priority interrupt is serviced, if several interrupts have the same software priority then the interrupt with the highest hardware priority is serviced first. figure 21 describes this decision process. figure 21. priority decision process table 13. interrupt software priority levels interrupt software priority level i1 i0 level 0 (main) low high 10 level 1 01 level 2 00 level 3 (= interrupt disable) 11 ?iret? restore pc, x, a, cc stack pc, x, a, cc load i1:0 from interrupt sw reg. fetch next reset trap pending instruction i1:0 from stack load pc from interrupt vector y n y n y n interrupt has the same or a lower software priority the interrupt stays pending than current one interrupt has a higher software priority than current one execute instruction interrupt pending software different interrupts same highest hardware priority serviced priority highest software priority serviced
st72344xx st72345xx interrupts doc id 12321 rev 5 55/247 when an interrupt request is not serviced immediately, it is latched and then processed when its software priority combined with the hardware priority becomes the highest one. note: 1 the hardware priority is exclusive while the software one is not. this allows the previous process to succeed with only one interrupt. 2 tli, reset and trap can be considered as having the highest software priority in the decision process. different interrupt vector sources two interrupt source types are managed by the st7 interrupt controller: the non-maskable type (reset, trap) and the maskable type (external or from internal peripherals). non-maskable sources these sources are processed regardless of the state of the i1 and i0 bits of the cc register (see figure 20 ). after stacking the pc, x, a and cc registers (except for reset), the corresponding vector is loaded in the pc register and the i1 and i0 bits of the cc are set to disable interrupts (level 3). these sources allow the processor to exit halt mode. trap (non-maskable software interrupt) this software interrupt is serv iced when the trap instruction is executed. it will be serviced according to the flowchart in figure 20 . reset the reset source has the highest priority in the st7. this means that the first current routine has the highest software priority (level 3) and the highest hardware priority. see the reset chapter for more details. maskable sources maskable interrupt vector sources can be serviced if the corresponding interrupt is enabled and if its own interrupt software priority (in isprx registers) is higher than the one currently being serviced (i1 and i0 in cc register). if an y of these two conditions is false, the interrupt is latched and thus remains pending. external interrupts external interrupts allow the processor to exit from halt low-power mode. external interrupt sensitivity is software selectable through the external interrupt control register (eicr). external interrupt trigger ed on edge will be latched and the interrupt request automatically cleared upon entering the interrupt service routine. if several input pins of a group connected to the same interrupt line are selected simultaneously, these will be logically ored. peripheral interrupts usually the peripheral interrupts cause the mcu to exit from halt mode except those mentioned in the ?interrupt mapping? table. a peripheral interrupt occurs when a specific flag is set in the peripheral status registers and if the corresponding enable bit is set in the peripheral control register. the general sequence for clearing an interrupt is based on an access to the status register followed by a read or write to an associated register. note: the clearing sequence resets the internal latch. a pending interrupt (i.e. waiting for being serviced) will therefore be lost if the clear sequence is executed.
interrupts st72344xx st72345xx 56/247 doc id 12321 rev 5 8.3 interrupts and low-power modes all interrupts allow the processor to exit the wait low-power mode. on the contrary, only external and other specified interrupts allow the processor to exit from the halt modes (see column ?exit from halt? in ?int errupt mapping? table). when several pending interrupts are present while exiting halt mode, the first one se rviced can only be an interrupt with exit from halt mode capability and it is selected th rough the same decision process shown in figure 21 . note: if an interrupt, that is not able to exit from halt mode, is pending with the highest priority when exiting halt mode, this interrupt is serviced after the first one serviced. 8.4 concurrent & nested management the following figure 22 and figure 23 show two different interrupt management modes. the first is called concurrent mode and does not allow an interrupt to be interrupted, unlike the nested mode in figure 23 . the interrupt hardware priority is given in this order from the lowest to the highest: main, it4, it3, it2, it1, it0, tli. the software priority is given for each interrupt. warning: a stack overflow may occur without notifying the software of the failure. figure 22. concurrent interrupt management main it4 it2 it1 trap it1 main it0 i1 hardware priority software 3 3 3 3 3 3/0 3 11 11 11 11 11 11 / 10 11 rim it2 it1 it4 trap it3 it0 it3 i0 10 priority level used stack = 10 bytes
st72344xx st72345xx interrupts doc id 12321 rev 5 57/247 figure 23. nested interrupt management 8.5 interrupt register description 8.5.1 cpu cc register interrupt bits reset value: 111x 1010 (xah) bits 5, 3 = i1, i0 software interrupt priority these two bits indicate the current interrupt software priority. these two bits are set/cleared by hardware when entering in interrupt. the loaded value is given by the corresponding bits in the interrupt software priority registers (isprx). they can be also set/cleared by software with the rim, sim, halt, wfi, iret and push/pop instructions (see ?interrupt dedicated instruction set? table). main it2 trap main it0 it2 it1 it4 trap it3 it0 hardware priority 3 2 1 3 3 3/0 3 11 00 01 11 11 11 rim it1 it4 it4 it1 it2 it3 i1 i0 11 / 10 10 software priority level used stack = 20 bytes 7 0 11i1hi0nzc read/write table 14. interrupt software priority priority level i1 i0 level 0 (main) low high 10 level 1 0 1 level 2 0 0 level 3 (= interrupt disable (1) ) 1. trap and reset events can interrupt a level 3 program. 11
interrupts st72344xx st72345xx 58/247 doc id 12321 rev 5 8.5.2 interrupt software pr iority registers (isprx) reset value: 1111 1111 (ffh) these four registers contain the interrupt software priority of each interrupt vector. each interrupt vector (except reset and trap) has corresponding bits in these registers where its own software priority is stored. this correspondence is shown in the following table. each i1_x and i0_x bit value in the isprx registers has the same meaning as the i1 and i0 bits in the cc register. level 0 can not be written (i1_x=1, i0_x=0). in this case, the previously stored value is kept. (example: previous = cfh, write = 64h, result = 44h) the reset, and trap vectors have no software priorities. when one is serviced, the i1 and i0 bits of the cc register are both set. caution: if the i1_x and i0_x bits are modified while the interrupt x is executed the following behavior has to be considered: if the inte rrupt x is still pending (new inte rrupt or flag not cleared) and the new software priority is higher than the previous one, the interrupt x is re-entered. otherwise, the software priority stays unchanged up to the next interrupt request (after the iret of the interrupt x). 70 ispr0 i1_3 i0_3 i1_2 i0_2 i1_1 i0_1 i1_0 i0_0 ispr1 i1_7 i0_7 i1_6 i0_6 i1_5 i0_5 i1_4 i0_4 ispr2 i1_11 i0_11 i1_10 i0_10 i1_9 i0_9 i1_8 i0_8 ispr3 1 1 1 1 i1_13 i0_13 i1_12 i0_12 read/write (bits 7:4 of ispr3 are read only) table 15. interrupt vector addresses vector address isprx bits fffbh-fffah i1_0 and i0_0 bits* fff9h-fff8h i1_1 and i0_1 bits ... ... ffe1h-ffe0h i1_13 and i0_13 bits table 16. dedicated interrupt instruction set instruction new description function/example i1 h i0 n z c halt entering halt mode 1 0 iret interrupt routine return pop cc, a, x, pc i1 h i0 n z c jrm jump if i1:0=11 (level 3) i1:0=11 ? jrnm jump if i1:0<>11 i1:0<>11 ? pop cc pop cc from the stack mem => cc i1 h i0 n z c
st72344xx st72345xx interrupts doc id 12321 rev 5 59/247 note: during the execution of an interrupt routine, the halt, popcc, rim, sim and wfi instructions change the current software priority up to the next iret instruction or one of the previously mentioned instructions. rim enable interrupt (level 0 set) load 10 in i1:0 of cc 1 0 sim disable interrupt (level 3 set) load 11 in i1:0 of cc 1 1 trap software trap software nmi 1 1 wfi wait for interrupt 1 0 table 16. dedicated interrupt instruction set (continued) instruction new description function/example i1 h i0 n z c table 17. i nterrupt mapping no. source block description register label priority order exit from halt (1) 1. valid for halt and active-halt modes except for the mcc/rtc interrupt source wh ich exits from active-halt mode only and awu interrupt which exits from awufh mode only. address vector reset reset n/a highest priority lowest priority yes fffeh-ffffh trap/icd software or icd interrupt no fffch-fffdh 0 awu auto wakeup interrupt awucsr yes fffah-fffbh 1 mcc/rtc rtc time base interrupt mccsr yes fff8h-fff9h 2 ei0 external interrupt port pa3, pe1 n/a yes fff6h-fff7h 3 ei1 external interrupt port pf2:0 n/a yes fff4h-fff5h 4 ei2 external interrupt port pb3:0 n/a yes fff2h-fff3h 5 ei3 external interrupt port pb4 n/a yes fff0h-fff1h 6 i2c3sns i2c3sns address 3 interrupt i2c3ssr no ffeeh-ffefh 7 i2c3sns i2c3sns address 1 & 2 interrupt no ffech-ffedh 8 spi spi peripheral interrupts spisr yes (2) 2. exit from halt possible when spi is in slave mode. ffeah-ffebh 9 timer a timer a peripheral interrupts tasr no ffe8h-ffe9h 10 timer b timer b peripheral interrupts tbsr no ffe6h-ffe7h 11 sci sci peripheral interrupt scisr no ffe4h-ffe5h 12 avd auxiliary-voltage-detector interrupt sicsr no ffe2h-ffe3h 13 i 2 ci 2 c peripheral interrupt i2csrx no ffe0h-ffe1h
interrupts st72344xx st72345xx 60/247 doc id 12321 rev 5 8.6 external interrupts 8.6.1 i/o port in terrupt sensitivity the external interrupt sensitivity is controlled by the ipa, ipb and isxx bits of the eicr register ( figure 24 ). this control allows to have up to 4 fully independent external interrupt source sensitivities. each external interrupt source can be generated on four (or five) different events on the pin: falling edge rising edge falling and rising edge falling edge and low level rising edge and high level (only for ei0 and ei2) to guarantee correct functionality, the sensitivity bits in the eicr register can be modified only when the i1 and i0 bits of the cc register are both set to 1 (level 3). this means that interrupts must be disabled before changing sensitivity. the pending interrupts are cleared by writing a different value in the isx[1:0], ipa or ipb bits of the eicr. figure 24. external interrupt control bits is10 is11 eicr sensitivity control pbor.3 pbddr.3 ipb bit pb3 ei2 interrupt source port b [3:0] interrupts pb3 pb2 pb1 pb0 is10 is11 eicr sensitivity control pbor.4 pbddr.4 pb4 ei3 interrupt source port b4 interrupt pb4 is20 is21 eicr sensitivity control paor.3 paddr.3 ipa bit pa3 ei0 interrupt source port a3, e1 interrupts is20 is21 eicr sensitivity control pfor.2 pfddr.2 pf2 ei1 interrupt source port f [2:0] interrupts pf2 pf1 pf0 pe1 pa3
st72344xx st72345xx interrupts doc id 12321 rev 5 61/247 8.7 external interrupt control register (eicr) reset value: 0000 0000 (00h) bits 7:6 = is1[1:0] ei2 and ei3 sensitivity the interrupt sensitivity, defined using the is1[1:0] bits, is applied to the following external interrupts: ei2 (port b3..0) ei3 (port b4) these 2 bits can be written only when i1 and i0 of the cc register are both set to 1 (level 3). bit 5 = ipb interrupt polarity for port b this bit is used to invert the sensitivity of the port b [3:0] external interrupts. it can be set and cleared by software only when i1 and i0 of the cc register are both set to 1 (level 3). 0: no sensitivity inversion 1: sensitivity inversion 7 0 is11 is10 ipb is21 is20 ipa 0 0 read/write table 18. external interrupt sensitivity (ei2) is11 is10 sensitivity ipb bit =0 ipb bit =1 0 0 falling edge & low level rising edge & high level 0 1 rising edge only falling edge only 1 0 falling edge only rising edge only 1 1 rising and falling edge table 19. external interrupt sensitivity (ei3) is11 is10 sensitivity 0 0 falling edge & low level 0 1 rising edge only 1 0 falling edge only 1 1 rising and falling edge
interrupts st72344xx st72345xx 62/247 doc id 12321 rev 5 bits 4:3 = is2[1:0] ei0 and ei1 sensitivity the interrupt sensitivity, defined using the is2[1:0] bits, is applied to the following external interrupts: ei0 (port a3, port e1) ei1 (port f2..0) these 2 bits can be written only when i1 and i0 of the cc register are both set to 1 (level 3). bit 2 = ipa interrupt polarity for ports a3 and e1 this bit is used to invert the sensitivity of the port a3 and e1 external interrupts. it can be set and cleared by software only when i1 and i0 of the cc register are both set to 1 (level 3). 0: no sensitivity inversion 1: sensitivity inversion bits 1:0 = reserved, must always be kept cleared. table 20. external interrupt sensitivity (ei0) is21 is20 sensitivity ipa bit =0 ipa bit =1 0 0 falling edge & low level rising edge & high level 0 1 rising edge only falling edge only 1 0 falling edge only rising edge only 1 1 rising and falling edge table 21. external interrupt sensitivity (ei1) is21 is20 sensitivity 0 0 falling edge & low level 0 1 rising edge only 1 0 falling edge only 1 1 rising and falling edge
st72344xx st72345xx interrupts doc id 12321 rev 5 63/247 table 22. nested interrupts register map and reset values address (hex.) register label 76543210 0024h ei1 ei0 mcc + si awu ispr0 reset value i1_3 1 i0_3 1 i1_2 1 i0_2 1 i1_1 1 i0_1 1 i1_0 1 i0_0 1 0025h i2c3sns i2c3sns ei3 ei2 ispr1 reset value i1_7 1 i0_7 1 i1_6 1 i0_6 1 i1_5 1 i0_5 1 i1_4 1 i0_4 1 0026h sci timer b timer a spi ispr2 reset value i1_11 1 i0_11 1 i1_10 1 i0_10 1 i1_9 1 i0_9 1 i1_8 1 i0_8 1 0027h ispr3 reset value1111 i2c avd i1_13 1 i0_13 1 i1_12 1 i0_12 1 0028h eicr reset value is11 0 is10 0 ipb 0 is21 0 is20 0 ipa 000
power-saving modes st72344xx st72345xx 64/247 doc id 12321 rev 5 9 power-saving modes 9.1 introduction to give a large measure of flexibility to the ap plication in terms of power consumption, five main power saving modes are implemented in the st7 (see figure 25 ): slow wait (and slow-wait) active-halt auto-wakeup from halt (awufh) halt after a reset the normal operating mode is selected by default (run mode). this mode drives the device (cpu and embedded periphera ls) by means of a master clock which is based on the main osc illator frequency divided or multiplied by 2 (f osc2 ). from run mode, the different power saving modes may be selected by setting the relevant register bits or by calling the specific st7 software instructi on whose action depends on the oscillator status. figure 25. power saving mode transitions power consumption wait slow run active-halt high low slow-wait auto-wakeup from halt halt
st72344xx st72345xx power-saving modes doc id 12321 rev 5 65/247 9.2 slow mode this mode has two targets: to reduce power consumption by decreasing the internal clock in the device, to adapt the internal clock frequency (f cpu ) to the available supply voltage. slow mode is controlled by three bits in the mccsr register: the sms bit which enables or disables slow mode and two cpx bits which select the internal slow frequency (f cpu ). in this mode, the master clock frequency (f osc2 ) can be divided by 2, 4, 8 or 16. the cpu and peripherals are clocked at this lower frequency (f cpu ). note: slow-wait mode is activated by entering wait mode while the device is in slow mode. figure 26. slow mode clock transitions 9.3 wait mode wait mode places the mcu in a low-power consumption mode by stopping the cpu. this power saving mode is selected by calling the ?wfi? instruction. all peripherals remain active. during wait mode, the i[1:0] bits of the cc register are forced to ?10?, to enable all interrupts. all other registers and memory remain unchanged. the mcu remains in wait mode until an interrupt or reset occurs, whereupon the program counter branches to the starting address of the interrupt or reset service routine. the mcu will remain in wait mode until a reset or an interrupt occurs, causing it to wake up. refer to figure 27 . 00 01 sms cp1:0 f cpu new slow normal run mode mccsr frequency request request f osc2 f osc2 /2 f osc2 /4 f osc2
power-saving modes st72344xx st72345xx 66/247 doc id 12321 rev 5 figure 27. wait mode flowchart note: 1 before servicing an interrupt, the cc register is pushed on the stack. the i[1:0] bits of the cc register are set to the current software priority level of the interrupt routine and recovered when the cc register is popped. 9.4 halt mode the halt mode is the lowest power consumption mode of the mcu. it is entered by executing the ?halt? instruction when the oie bit of the main clock controller status register (mccsr) is cleared (see section 11.2 on page 88 for more details on the mccsr register) and when the awuen bit in the awucsr register is cleared. the mcu can exit halt mode on reception of either a specific interrupt (see ta bl e 1 7 : interrupt mapping on page 59 ) or a reset. when exiting halt mode by means of a reset or an interrupt, the oscillator is im mediately turned on and the 256 or 4096 cpu cycle delay is used to stabilize the oscillator. after the st art up delay, the cpu resumes operation by servicing the interrupt or by fetching the reset vector which woke it up (see figure 29 ). when entering halt mode, the i[1:0] bits in the cc register are forced to ?10b?to enable interrupts. therefore, if an interrupt is pending, the mcu wakes up immediately. in halt mode, the main oscillator is turned off causing all intern al processing to be stopped, including the operation of the on-chip peripherals. all peripherals are not clocked except the ones which get their clock supply from another clock generator (such as an external or auxiliary oscillator). the compatibility of watc hdog operation with halt mode is configured by the ?wdghalt? option bit of the option byte. the halt instruction when executed while the watchdog wfi instruction reset interrupt y n n y cpu oscillator peripherals i[1:0] bits on on 10 off fetch reset vector or service interrupt cpu oscillator peripherals i[1:0] bits on off 10 on cpu oscillator peripherals i[1:0] bits on on xx (1) on 256 or 4096 cpu clock cycle delay
st72344xx st72345xx power-saving modes doc id 12321 rev 5 67/247 system is enabled, can generate a watchdog reset (see section 11.1 on page 82 for more details). figure 28. halt timing overview figure 29. halt mode flowchart note: 1 wdghalt is an option bit. see option byte section for more details. 2 peripheral clocked with an external clock source can still be active. 3 only some specific interrupts can exit the mcu from halt mode (such as external interrupt). refer to table 17: interrupt mapping on page 59 for more details. 4 before servicing an interrupt, the cc register is pushed on the stack. the i[1:0] bits of the cc register are set to the current software priority level of the interrupt routine and recovered when the cc register is popped. halt run run 256 or 4096 cpu cycle delay reset or interrupt halt instruction fetch vector [mccsr.oie=0] reset interrupt 3) y n n y cpu oscillator peripherals 2) i[1:0] bits off off 10 off fetch reset vector or service interrupt cpu oscillator peripherals i[1:0] bits on off xx 4) on cpu oscillator peripherals i[1:0] bits on on xx 4) on 256 or 4096 cpu clock delay watchdog enable disable wdghalt 1) 0 watchdog reset 1 cycle halt instruction (mccsr.oie=0) (awucsr.awuen=0)
power-saving modes st72344xx st72345xx 68/247 doc id 12321 rev 5 halt mode recommendations make sure that an external event is available to wake up the microcontroller from halt mode. when using an external interrupt to wake up the microcontroller, reinitialize the corresponding i/o as ?input pull-up with interrupt? before executing the halt instruction. the main reason for this is that the i/o may be wrongly configured due to external interference or by an unforeseen logical condition. for the same reason, reinitialize the level sens itiveness of each external interrupt as a precautionary measure. the opcode for the halt instruction is 0x8e . to avoid an unexpected halt instruction due to a program counter failure, it is advised to clear all occurrences of the data value 0x8e from memory. for example, avoid defining a constant in rom with the value 0x8e. as the halt instruction clears the interrupt ma sk in the cc register to allow interrupts, the user may choose to clear all pending interrupt bits before executing the halt instruction. this avoids entering other peripheral interrupt routines after executing the external interrupt routine corresponding to the wake-up event (reset or external interrupt). 9.5 active-halt mode active-halt mode is the lowest power consumption mode of the mcu with a real-time clock available. it is entered by executing the ?ha lt? instruction when mcc/rtc interrupt enable flag (oie bit in mccsr register) is set and when the awuen bit in the awucsr register is cleared (see register description on page 72 ). the mcu can exit active-halt mode on reception of the rtc interrupt and some specific interrupts (see table 17: interrupt mapping on page 59 ) or a reset. when exiting active-halt mode by means of a reset a 4096 or 256 cpu cycle delay occurs (depending on the option byte). after the start up delay, the cpu resumes operation by servicing the interrupt or by fetching the reset vector which woke it up (see figure 31 ). when entering active-halt mode, the i[1:0] bits in the cc register are cleared to enable interrupts. therefore, if an interrupt is pending, the mcu wakes up immediately. in active-halt mode, only the main oscillato r and its associated counter (mcc/rtc) are running to keep a wake-up time base. all ot her peripherals are not clocked except those which get their clock supply from another cloc k generator (such as external or auxiliary oscillator). the safeguard against staying locked in active-halt mode is provided by the oscillator interrupt. table 23. power saving mode mccsr oie bit power saving mode entered when halt instruction is executed 0 halt mode 1 active-halt mode
st72344xx st72345xx power-saving modes doc id 12321 rev 5 69/247 note: as soon as active halt is enabled, executing a halt instruction while the watchdog is active does not generate a reset. this means that the device cannot spend more than a defined delay in this power saving mode. figure 30. active-halt timing overview figure 31. active-halt mode flowchart note: 1 this delay occurs only if the mcu exits active-halt mode by means of a reset. 2 peripheral clocked with an external clock source can still be active. 3 only the rtc interrupt and some specific interrupts can exit the mcu from active-halt mode (such as external interrupt). refer to table 17 on page 59 for more details. 4 before servicing an interrupt, the cc register is pushed on the stack. the i[1:0] bits in the cc register are set to the current software priority level of the interrupt routine and restored when the cc register is popped. halt run run 256 or 4096 cycle delay (after reset) reset or interrupt halt instruction fetch vector active- (active-halt enabled) halt instruction reset interrupt 3) y n n y cpu oscillator peripherals 2) i[1:0] bits on off 10 off fetch reset vector or service interrupt cpu oscillator peripherals i[1:0] bits on off xx 4) on cpu oscillator peripherals i[1:0] bits on on xx 4) on 256 or 4096 cpu clock cycle delay (mccsr.oie=1) (awucsr.awuen=0)
power-saving modes st72344xx st72345xx 70/247 doc id 12321 rev 5 9.6 auto-wakeup from halt mode auto-wakeup from halt (awufh) mode is similar to halt mode with the addition of an internal rc oscillator for wake -up. compared to active-hal t mode, awufh has lower power consumption because the main clock is not kept running, but there is no accurate real-time clock available. it is entered by executing the halt inst ruction when the awuen bit in the awucsr register has been set and the oie bit in the mccsr register is cleared (see section 11.2 on page 88 for more details). figure 32. awufh mode block diagram as soon as halt mode is entered, and if the awuen bit has been set in the awucsr register, the awu rc oscillator provides a clock signal (f awu_rc ). its frequency is divided by a fixed divider and a programmable prescaler controlled by the awupr register. the output of this prescaler provides the delay time. when the delay has elapsed the awuf flag is set by hardware and an interrupt wakes-up the mcu from halt mode. at the same time the main oscillator is immediately turned on and a 256 or 4096 cycle delay is used to stabilize it. after this startup delay, the cpu resumes operation by servicing the awufh interrupt. the awu flag and its associated interrupt are cleared by software reading the awucsr register. to compensate for any frequency dispersion of the awu rc oscillator, it can be calibrated by measuring the clock frequency f awu_rc and then calculating the right prescaler value. measurement mode is enabled by setting the awum bit in the awucsr register in run mode. this connects internally f awu_rc to the icap2 input of the 16-bit timer a, allowing the f awu_rc to be measured using the main oscillator cloc k as a reference timebase. similarities with halt mode the following awufh mode behavior is the same as normal halt mode: the mcu can exit awufh mode by means of any interrupt with exit from halt capability or a reset (see section 9.4: halt mode on page 66 ). when entering awufh mode, the i[1:0] bits in the cc register are forced to 10b to enable interrupts. therefore, if an interrupt is pending, the mcu wakes up immediately. in awufh mode, the main oscilla tor is turned off causing a ll internal processing to be stopped, including the operation of the on-chip peripherals. none of the peripherals are clocked except those which get their clock supply from another clock generator (such as an external or auxiliary oscillator like the awu oscillator). the compatibility of watchdog operation with awufh mode is configured by the wdghalt option bit in the option byte. depending on this setting, the halt instruction when executed while the watchdog system is enabled, can generate a watchdog reset. awu rc awufh f awu_rc awufh oscillator prescaler interrupt /64 divider to timer input capture /1 .. 255
st72344xx st72345xx power-saving modes doc id 12321 rev 5 71/247 figure 33. awuf halt timing diagram figure 34. awufh mode flowchart 1. wdghalt is an option bit. see option byte section for more details. 2. peripheral clocked with an external clock source can still be active. 3. only an awufh interrupt and some specific interrupts can exit the mcu from halt mode (such as external interrupt). refer to table 17: interrupt mapping on page 59 for more details. 4. before servicing an interrupt, the cc register is pushed on the stack. the i[1:0] bits of the cc register are set to the current software priority level of the inte rrupt routine and recovered when the cc register is popped. awufh interrupt f cpu run mode halt mode 256 or 4096 t cpu run mode f awu_rc clear by software t awu reset interrupt (3) y n n y cpu main osc peripherals (2) i[1:0] bits off off 10 off fetch reset vector or service interrupt cpu main osc peripherals i[1:0] bits on off xx (4) on cpu main osc peripherals i[1:0] bits on on xx (4) on 256 or 4096 cpu clock delay watchdog enable disable wdghalt (1) 0 watchdog reset 1 cycle awu rc osc on awu rc osc off awu rc osc off halt instruction (mccsr.oie=0) (awucsr.awuen=1)
power-saving modes st72344xx st72345xx 72/247 doc id 12321 rev 5 9.7 register description 9.7.1 awufh control/status register (awucsr) reset value: 0000 0000 (00h) bits 7:3 = reserved. bit 2= awuf auto-wakeup flag this bit is set by hardware when the awu module generates an interrupt and cleared by software on reading awucsr. 0: no awu interrupt occurred 1: awu interrupt occurred bit 1= awum auto-wakeup measurement this bit enables the awu rc oscillator and co nnects internally it s output to the icap2 input of 16-bit timer a. this allows the timer to be used to measure the awu rc oscillator dispersion and then compensate this dispersion by providing the right value in the awupr register. 0: measurement disabled 1: measurement enabled bit 0 = awuen auto-wakeup from halt enabled this bit enables the auto-wakeup from halt feature: once halt mode is entered, the awufh wakes up the microcontroller after a time delay defined by the awu prescaler value. it is set and cleared by software. 0: awufh (auto-wakeup from halt) mode disabled 1: awufh (auto-wakeup from halt) mode enabled 7 0 00000 awu f awum awuen read/write (except bit 2 read only)
st72344xx st72345xx power-saving modes doc id 12321 rev 5 73/247 9.7.2 awufh prescaler register (awupr) reset value: 1111 1111 (ffh) bits 7:0= awupr[7:0] auto-wakeup prescaler these 8 bits define the awupr dividing factor (as explained below: in awu mode, the period that th e mcu stays in halt mode (t awu in figure 33 ) is defined by this prescaler register can be programmed to modify the time that the mcu stays in halt mode before waking up automatically. 7 0 awupr7 awupr6 awupr5 awupr4 awupr3 awupr2 awupr1 awupr0 read/write table 24. awupr dividing factor awupr[7:0 ] dividing factor 00h forbidden (1) 1. if 00h is written to awupr, depending on the product, an interrupt is generated immediately after a halt instruction, or the awupr remains unchanged. 01h 1 ... ... feh 254 ffh 255 t awu 64 awupr 1 f awurc ------------------------- -t rcstrt + = table 25. awu register map and reset values address (hex.) register label 7654321 0 002eh awucsr reset value 00000 awuf 0 awum 0 awuen 0 002fh awupr reset value awupr7 1 awupr6 1 awupr5 1 awupr4 1 awupr3 1 awupr2 1 awupr1 1 awupr0 1
i/o ports st72344xx st72345xx 74/247 doc id 12321 rev 5 10 i/o ports 10.1 introduction the i/o ports offer different functional modes: transfer of data through digital inputs and outputs and for specific pins: external interrupt generation alternate signal input/output for the on-chip peripherals. an i/o port contains up to 8 pins. each pin can be programmed independently as digital input (with or without interrupt generation) or digital output. 10.2 functional description each port has two main registers: data register (dr) data direction register (ddr) and one optional register: option register (or) each i/o pin may be programmed using the corresponding register bits in the ddr and or registers: bit x corresponding to pin x of the port. the same correspondence is used for the dr register. the following description takes into account the or register, (for specific ports which do not provide this register refer to the i/o port implementation section). the generic i/o block diagram is shown in figure 35 . 10.2.1 input modes the input configuration is selected by clearing the corresponding ddr register bit. in this case, reading the dr register returns the digital value applied to the external i/o pin. different input modes can be selected by software through the or register. note: 1 writing the dr register modifies the latch value but does not affect the pin status. 2 when switching from input to output mode, the dr register has to be written first to drive the correct level on the pin as soon as the port is configured as an output. 3 do not use read/modify/write instructions (bset or bres) to modify the dr register as this might corrupt the dr content for i/os configured as input. external interrupt function when an i/o is configured as input with interrupt, an event on this i/o can generate an external interrupt request to the cpu. each pin can independently generate an interrupt request. the interrupt sensitivity is independently programmable using the sensitivity bits in the eicr register.
st72344xx st72345xx i/o ports doc id 12321 rev 5 75/247 each external interrupt vector is linked to a dedicated group of i/o port pins (see pinout description and interrupt section). if several input pins are selected simultaneously as interrupt sources, these are first detected according to the sensitivity bits in the eicr register and then logically ored. the external interrupts are hardware interrupts, which means that the request latch (not accessible directly by the application) is automatically cleared when the corresponding interrupt vector is fetched. to clear an unwanted pending interrupt by software, the sensitivity bits in the eicr register must be modified. 10.2.2 output modes the output conf iguration is selected by setting the co rresponding ddr regist er bit. in this case, writing the dr register applies this digital value to the i/o pin through the latch. then reading the dr register returns the previously stored value. two different output modes can be selected by software through the or register: output push-pull and open-drain. dr register value and output pin status: 10.2.3 alternate functions when an on-chip peripheral is configured to use a pin, the alternate function is automatically selected. this alternate function takes priority over the standard i/o programming. when the signal is coming from an on-chip peripheral, the i/o pin is automatically configured in output mode (push-pull or open drain according to the peripheral). when the signal is going to an on-chip peripheral, the i/o pin must be configured in input mode. in this case, the pin state is also digi tally readable by addressing the dr register. note: input pull-up configuration can cause unexpected value at the input of the alternate peripheral input. when an on-chip peripheral use a pin as input and output, this pin has to be configured in input floating mode. table 26. output modes dr push-pull open-drain 0v ss v ss 1v dd floating
i/o ports st72344xx st72345xx 76/247 doc id 12321 rev 5 figure 35. i/o port general block diagram table 27. i/o port mode options (1) 1. ni = not implemented, off = implemented not activated, on = implemented and activated. configuration mode pull-up p-buffer diodes to v dd to v ss input floating with/without interrupt off off on on pull-up with/without interrupt on output push-pull off on open drain (logic level) off true open drain ni ni ni (2) 2. the diode to vdd is not implemented in the tr ue open drain pads. a local protection between the pad and vss is implemented to protect the device against positive stress. dr ddr or data bus pad v dd alternate enable alternate output 1 0 or sel ddr sel dr sel pull-up condition p-buffer (see table below) n-buffer pull-up (see table below) 1 0 analog input if implemented alternate input v dd diodes (see table below) external source (ei x ) interrupt cmos schmitt trigger register access
st72344xx st72345xx i/o ports doc id 12321 rev 5 77/247 caution: the alternate function must not be activated as long as the pin is configured as input with interrupt, in order to avoid generating spurious interrupts. analog alternate function when the pin is used as an adc input, the i/o must be configured as floating input. the analog multiplexer (controlled by the adc registers) switches the analog voltage present on the selected pin to the common analog rail which is connected to the adc input. table 28. i/o port configurations hardware configuration input (1) 1. when the i/o port is in input configuration and the associated alternate function is enabled as an output, reading the dr register will read th e alternate function output status. open-drain output (2) 2. when the i/o port is in output configuration and t he associated alternate func tion is enabled as an input, the alternate function reads the pin stat us given by the dr register content. push-pull output (2) condition pad v dd r pu external interrupt data bus pull-up interrupt dr register access w r source (ei x ) dr register condition alternate input not implemented in true open drain i/o ports analog input pad r pu data bus dr dr register access r/w v dd alternate alternate enable output register not implemented in true open drain i/o ports pad r pu data bus dr dr register access r/w v dd alternate alternate enable output register not implemented in true open drain i/o ports
i/o ports st72344xx st72345xx 78/247 doc id 12321 rev 5 it is recommended not to change the voltage level or loading on any port pin while conversion is in progress. furthermore it is recommended not to have clocking pins located close to a selected analog pin. warning: the analog input voltage level must be within the limits stated in the absolute maximum ratings. 10.3 i/o port implementation the hardware implementation on each i/o port depends on the settings in the ddr and or registers and specific feature of the i/o port such as adc input or true open drain. switching these i/o ports from one state to another should be done in a sequence that prevents unwanted side effects. recommend ed safe transitions are illustrated in figure 36 on page 78 . other transitions are potentially risky and should be avoided, since they are likely to present unwanted side-effects such as spurious interrupt generation. figure 36. interrupt i/o port state transitions 10.4 low-power modes 10.5 interrupts the external interrupt event generates an interrupt if the corresponding configuration is selected with ddr and or registers and the interrupt mask in the cc register is not active (rim instruction). 01 floating/pull-up interrupt input 00 floating (reset state) input 10 open-drain output 11 push-pull output xx = ddr, or table 29. description mode description wait no effect on i/o ports. external interrupts cause the device to exit from wait mode. halt no effect on i/o ports. external interrupts cause the device to exit from halt mode. table 30. description of interrupt events interrupt event event flag enable control bit exit from wait exit from halt external interrupt on selected external event - ddrx orx ye s
st72344xx st72345xx i/o ports doc id 12321 rev 5 79/247 10.5.1 i/o port implementation the i/o port register configurations are summarized as follows. standard ports: pa[5:4], pc[7:0], pd[5:0], pe0, pf[7:6], pf4 interrupt ports: pb4, pb[2:0], pf[1:0] (with pull-up) pa3, pe1, pb3, pf2 (without pull-up) true open-drain ports: pa[7:6], pd[7:6] table 31. i/o port register configurations (standard ports) mode ddr or floating input 0 0 pull-up input 0 1 open drain output 1 0 push-pull output 1 1 table 32. i/o port register configurations (interrupt ports with pull-up) mode ddr or floating input 0 0 pull-up interrupt input 0 1 open drain output 1 0 push-pull output 1 1 table 33. i/o port register configurations (interrupt ports without pull-up) mode ddr or floating input 0 0 floating interrupt input 0 1 open drain output 1 0 push-pull output 1 1 table 34. i/o port register configurations (true open drain ports) mode ddr floating input 0 open drain (high sink ports) 1
i/o ports st72344xx st72345xx 80/247 doc id 12321 rev 5 caution: in small packages, an internal pull-up is applied permanently to the non-bonded i/o pins. so they have to be kept in input floating configuration to avoid unwanted consumption. table 35. port configuration port pin name input output or = 0 or = 1 or = 0 or = 1 port a pa7:6 floating true open-drain pa5:4 floating pull-up open drain push-pull pa3 floating floating interrupt open drain push-pull port b pb3 floating floating interrupt open drain push-pull pb4, pb2:0 floating pull-up interrupt open drain push-pull port c pc7:0 floating pull-up open drain push-pull port d pd7:6 floating true open-drain pd5:0 floating pull-up open drain push-pull port e pe1 floating floating interrupt open drain push-pull pe0 floating pull-up open drain push-pull port f pf7:6, 4 floating pull-up open drain push-pull pf2 floating floating interrupt open drain push-pull pf1:0 floating pull-up interrupt open drain push-pull table 36. i/o port register map and reset values address (hex.) register label 76543210 reset value of all i/o port registers 00000000 0000h padr msb lsb 0001h paddr 0002h paor 0003h pbdr msb lsb 0004h pbddr 0005h pbor 0006h pcdr msb lsb 0007h pcddr 0008h pcor 0009h pddr msb lsb 000ah pdddr 000bh pdor
st72344xx st72345xx i/o ports doc id 12321 rev 5 81/247 000ch pedr msb lsb 000dh peddr 000eh peor 000fh pfdr msb lsb 0010h pfddr 0011h pfor table 36. i/o port register map and reset values (continued) address (hex.) register label 76543210
on-chip peripherals st72344xx st72345xx 82/247 doc id 12321 rev 5 11 on-chip peripherals 11.1 window watchdog (wwdg) 11.1.1 introduction the window watchdog is used to detect the occurrence of a software fault, usually generated by external interference or by unforeseen logical conditions, which causes the application program to abandon its normal sequence. the watchdog circuit generates an mcu reset on expiry of a programmed time period, unless the program refreshes the contents of the downcounter before the t6 bit becomes cleared. an mcu reset is also generated if the 7-bit downcounter value (in the control register) is refreshed before the downcounter has reached the window register value. this implies that the counter must be refreshed in a limited window. 11.1.2 main features programmable free-running downcounter conditional reset ? reset (if watchdog activated) when the downcounter value becomes less than 40h ? reset (if watchdog activated) if the downcounter is reloaded outside the window (see figure 40 ) hardware/software watchdog activation (selectable by option byte) optional reset on halt instruction (configurable by option byte) 11.1.3 functional description the counter value stored in the wdgcr register (bits t[6:0]), is decremented every 16384 f osc2 cycles (approx.), and the length of the timeout period can be programmed by the user in 64 increments. if the watchdog is activated (the wdga bit is set) and when the 7-bit downcounter (t[6:0] bits) rolls over from 40h to 3fh (t6 becomes cl eared), it initiates a re set cycle pulling low the reset pin for typically 30 s. if the software reloads the counter while the counter is greater than the value stored in the window register, then a reset is generated.
st72344xx st72345xx on-chip peripherals doc id 12321 rev 5 83/247 figure 37. watchdog block diagram the application program must write in the wd gcr register at regular intervals during normal operation to prevent an mcu reset. this operation must occur only when the counter value is lower than the window register value. the value to be stored in the wdgcr register must be between ffh and c0h (see figure 38 ): enabling the watchdog: when software watchdog is selected (by option byte), the watchdog is disabled after a reset. it is enabled by setting the wdga bit in the wdgcr register, then it cannot be disabled again except by a reset. when hardware watchdog is selected (by opti on byte), the watchdog is always active and the wdga bit is not used. controlling the downcounter: this downcounter is free-running: it counts down even if the watchdog is disabled. when the watchdog is enabled, the t6 bit must be set to prevent generating an immediate reset. the t[5:0] bits contain the number of increments which represents the time delay before the watchdog produces a reset (see figure 38: approximate timeout duration ). the timing varies between a minimum and a maximum value due to the unknown status of the prescaler when writing to the wdgcr register (see figure 39 ). the window register (wdgwr) contains the high limit of the window: to prevent a reset, the downcounter must be reloaded when its value is lower than the window register value and greater than 3fh. figure 40 describes the window watchdog process. reset wdga 6-bit downcounter (cnt) t6 t0 watchdog control register (wdgcr) t1 t2 t3 t4 t5 - w6 w0 watchdog window register (wdgwr) w1 w2 w3 w4 w5 comparator t6:0 > w6:0 cmp = 1 when write wdgcr wdg prescaler div 4 f osc2 12-bit mcc rtc counter msb lsb div 64 0 5 6 11 mcc/rtc tb[1:0] bits (mccsr register)
on-chip peripherals st72344xx st72345xx 84/247 doc id 12321 rev 5 note: the t6 bit can be used to generate a software reset (the wdga bit is set and the t6 bit is cleared). watchdog reset on halt option if the watchdog is activated and the watchdog reset on halt option is selected, then the halt instruction will generate a reset. 11.1.4 using halt mode with the wdg if halt mode with watchdog is enabled by option byte (no watchdog reset on halt instruction), it is recommended before executing the halt instruction to refresh the wdg counter, to avoid an unexpected wdg reset immediately after waking up the microcontroller. 11.1.5 how to program the watchdog timeout figure 38 shows the linear relationship between the 6-bit value to be loaded in the watchdog counter (cnt) and the resulting timeout durati on in milliseconds. this can be used for a quick calculation without taking the timing variat ions into account. if more precision is needed, use the formulae in figure 39 . caution: when writing to the wdgcr register, always write 1 in the t6 bit to avoid generating an immediate reset. figure 38. approximate timeout duration cnt value (hex.) watchdog timeout (ms) @ 8 mhz f osc2 3f 00 38 128 1.5 65 30 28 20 18 10 08 50 34 18 82 98 114
st72344xx st72345xx on-chip peripherals doc id 12321 rev 5 85/247 figure 39. exact timeout duration (t min and t max ) where : t min0 = (lsb + 128) x 64 x t osc2 t max0 = 16384 x t osc2 t osc2 = 125 ns if f osc2 =8 mhz cnt = value of t[5:0] bits in the wdgcr register (6 bits) msb and lsb are values from the table below depending on the timebase selected by the tb[1:0] bits in the mccsr register to calculate the minimum watchdog timeout (t min ): to calculate the maximum watchdog timeout (t max ): note: in the above formulae, division results must be rounded down to the next integer value. example: with 2 ms timeout selected in mccsr register tb1 bit (mccsr reg.) tb0 bit (mccsr reg.) selected mccsr time base msb lsb 002 ms 459 014 ms 853 1 0 10 ms 20 35 1 1 25 ms 49 54 if then else if then else value of t[5:0] bits in wdgcr register (hex.) min. watchdog timeout (ms) t min max. watchdog timeout (ms) t max 00 1.496 2.048 3f 128 128.552 cnt msb 4 ------------- < t min t min0 16384 cnt t osc2 + = t min t min0 16384 cnt 4cnt msb ---------------- - ? ?? ?? 192 lsb + () 64 4cnt msb ---------------- - + t osc2 + = cnt msb 4 ------------- t max t max0 16384 cnt t osc2 + = t max t max0 16384 cnt 4cnt msb ---------------- - ? ?? ?? 192 lsb + () 64 4cnt msb ---------------- - + t osc2 + =
on-chip peripherals st72344xx st72345xx 86/247 doc id 12321 rev 5 figure 40. window watchdog timing diagram 11.1.6 low-power modes t6 bit reset wdgwr t[5:0] cnt downcounter time refresh window refresh not allowed (step = 16384/f osc2 ) 3fh table 37. descriptions mode description slow no effect on watchdog: the downcounter continues to decrement at normal speed. wait no effect on watchdog: the do wncounter continues to decrement. halt oie bit in mccsr register wdghalt bit in option byte 00 no watchdog reset is generated. the mcu enters halt mode. the watchdog counter is decremented once and then stops counting and is no longer able to generate a watchdog reset until the mcu receives an external interrupt or a reset. if an interrupt is received (refer to interrupt table mapping to see interrupts which can occur in halt mode), the watchdog restarts counting after 256 or 4096 cpu clocks. if a reset is generated, the watchdog is disabled (reset state) unless hardware watchdog is selected by option byte. for application recommendations see section 11.1.8 below. 0 1 a reset is generated instead of entering halt mode. active-halt 1 x no reset is generated. the mcu enters active halt mode. the watchdog counter is no t decremented. it stop counting. when the mcu receives an oscillator interrupt or external interrupt, the watchdog restarts counting immediately. when the mcu receives a reset the watchdog restarts counting after 256 or 4096 cpu clocks.
st72344xx st72345xx on-chip peripherals doc id 12321 rev 5 87/247 11.1.7 hardware watchdog option if hardware watchdog is selected by option byte, the watchdog is always active and the wdga bit in the wdgcr is not used. refer to the option byte description. 11.1.8 using halt mode with the wdg (wdghalt option) the following recommendation applies if halt mode is used when the watchdog is enabled. before executing the halt instruction, refresh the wdg counter, to avoid an unexpected wdg reset immediately after waking up the microcontroller. 11.1.9 interrupts none. 11.1.10 register description control register (wdgcr) reset value: 0111 1111 (7fh) bit 7 = wdga activation bit. this bit is set by software and only cleared by hardware after a reset. when wdga = 1, the watchdog can generate a reset. 0: watchdog disabled 1: watchdog enabled note: this bit is not used if the hardware watchdog option is enabled by option byte. bits 6:0 = t[6:0] 7-bit counter (msb to lsb) . these bits contain the value of the watchdog counter. it is decremented every 16384 f osc2 cycles (approx.). a reset is produced w hen it rolls over from 40h to 3fh (t6 becomes cleared). window register (wdgwr) reset value: 0111 1111 (7fh) bit 7 = reserved bits 6:0 = w[6:0] 7-bit window value these bits contain the window value to be compared to the downcounter. 7 0 wdga t6 t5 t4 t3 t2 t1 t0 read/write 7 0 - w6w5w4w3w2w1w0 read/write
on-chip peripherals st72344xx st72345xx 88/247 doc id 12321 rev 5 11.2 main clock controller wi th real-time clock and beeper (mcc/rtc) the main clock controller consists of three different functions: a programmable cpu clock prescaler a clock-out signal to supply external devices a real-time clock timer with interrupt capability each function can be used independently and simultaneously. 11.2.1 programmable cpu clock prescaler the programmable cpu clock prescaler supplies the clock for the st7 cpu and its internal peripherals. it manages slow power-saving mode (see section 9.2: slow mode for more details). the prescaler selects the f cpu main clock frequency and is controlled by three bits in the mccsr register: cp[1:0] and sms. 11.2.2 clock-out capability the clock-out capability is an alternate function of an i/o port pin that outputs a f osc2 clock to drive external devices. it is controlled by the mco bit in the mccsr register. caution: when selected, the clock out pin suspends the clock during active-halt mode. 11.2.3 real-time clock timer (rtc) the counter of the real-time clock timer allows an interrupt to be generated based on an accurate real-time clock. four different time bases depending directly on f osc2 are available. the whole functionality is controlled by four bits of the mccsr register: tb[1:0], oie and oif. when the rtc interrupt is enabled (oie bit set), the st7 enters active-halt mode when the halt instruction is executed. see section 9.5: active-halt mode on page 68 for more details. 11.2.4 beeper the beep function is controlled by the mccbcr register. it can output three selectable frequencies on the beep pin (i/o port alternate function). table 38. watchdog timer register map and reset values address (hex.) register label 765 4 3210 2a wdgcr reset value wdga 0 t6 1 t5 1 t4 1 t3 1 t2 1 t1 1 t0 1 30 wdgwr reset value - 0 w6 1 w5 1 w4 1 w3 1 w2 1 w1 1 w0 1
st72344xx st72345xx on-chip peripherals doc id 12321 rev 5 89/247 figure 41. main clock controller (mcc/rtc) block diagram 11.2.5 low-power modes 11.2.6 interrupts the mcc/rtc interrupt event generates an interrupt if the oie bit of the mccsr register is set and the interrupt mask in the cc register is not active (rim instruction). div 2, 4, 8, 16 mcc/rtc interrupt sms cp1 cp0 tb1 tb0 oie oif cpu clock mccsr 12-bit mcc rtc counter to cpu and peripherals f osc2 f cpu mco mco bc1 bc0 mccbcr beep selection beep signal 1 0 to watchdog timer div 64 table 39. mode description mode description wait no effect on mcc/rtc peripheral. mcc/rtc interrupt cause the device to exit from wait mode. active-halt no effect on mcc/rtc counter (oie bit is set), the registers are frozen. mcc/rtc interrupt cause the device to exit from active-halt mode. halt mcc/rtc counter and registers are frozen. mcc/rtc operation resumes when the mcu is woken up by an interrupt with ?exit from halt? capability. table 40. interrupt event interrupt event event flag enable control bit exit from wait exit from halt time base overflow event oif oie yes no (1) 1. the mcc/rtc interrupt wakes up the mcu from active-halt mode, not from halt mode.
on-chip peripherals st72344xx st72345xx 90/247 doc id 12321 rev 5 11.2.7 register description mcc control/status register (mccsr) reset value: 0000 0000 (00h) bit 7 = mco main clock out selection this bit enables the mco alternate function on the pf0 i/o port. it is set and cleared by software. 0: mco alternate function disabled (i/o pin free for general-purpose i/o) 1: mco alternate function enabled (f cpu on i/o port) note: to reduce power consumption, the mco function is not active in active-halt mode. bits 6:5 = cp[1:0] cpu clock prescaler these bits select the cpu clock prescaler which is applied in the different slow modes. their action is conditioned by the setting of the sms bit. these two bits are set and cleared by software. bit 4 = sms slow mode select this bit is set and cleared by software. 0: normal mode. f cpu = f osc2 1: slow mode. f cpu is given by cp1, cp0 see section 9.2: slow mode and section 11.1: window watchdog (wwdg) on page 82 for more details. bits 3:2 = tb[1:0] time base control these bits select the programmable divider time base. they are set and cleared by software. 7 0 mco cp1 cp0 sms tb1 tb0 oie oif read/write table 41. cpu clock prescaler selection f cpu in slow mode cp1 cp0 f osc2 / 2 0 0 f osc2 / 4 0 1 f osc2 / 8 1 0 f osc2 / 16 1 1
st72344xx st72345xx on-chip peripherals doc id 12321 rev 5 91/247 a modification of the time base is taken into account at the end of the current period (previously set) to avoid an unwanted time shift. this allows to use this time base as a real- time clock. bit 1 = oie oscillator interrupt enable this bit set and cleared by software. 0: oscillator interrupt disabled 1: oscillator interrupt enabled this interrupt can be used to exit from active-halt mode. when this bit is set, calling the st7 softwar e halt instruction enters the active-halt power-saving mode . bit 0 = oif oscillator interrupt flag this bit is set by hardware and cleared by software reading the mccsr register. it indicates when set th at the main oscillato r has reached the selected elapsed time (tb1:0). 0: timeout not reached 1: timeout reached caution: the bres and bset instructions must not be used on the mccsr register to avoid unintentionally clearing the oif bit. mcc beep control register (mccbcr) reset value: 0000 0000 (00h) bits 7:2 = reserved, must be kept cleared. bits 1:0 = bc[1:0] beep control these 2 bits select th e pf1 pin beep capability. table 42. time base control counter prescaler time base tb1 tb0 f osc2 = 4 mhz f osc2 = 8 mhz 16000 4 ms 2 ms 0 0 32000 8 ms 4 ms 0 1 80000 20 ms 10 ms 1 0 200000 50 ms 25 ms 1 1 7 0 000000bc1bc0 read/write
on-chip peripherals st72344xx st72345xx 92/247 doc id 12321 rev 5 the beep output signal is available in active-halt mode but has to be disabled to reduce the consumption. table 43. beep control bc1 bc0 beep mode with f osc2 = 8 mhz 00 off 01 ~2-khz output beep signal ~50% duty cycle 10 ~1-khz 1 1 ~500-hz table 44. main clock controller register map and reset values address (hex.) register label 765 4 3 21 0 002bh sicsr reset value 0 avdie 0 avdf 0 lvdrf x locked 000 wdgrf x 002ch mccsr reset value mco 0 cp1 0 cp0 0 sms 0 tb1 0 tb0 0 oie 0 oif 0 002dh mccbcr reset value 0 0 0 0 0 0 bc1 0 bc0 0
st72344xx st72345xx on-chip peripherals doc id 12321 rev 5 93/247 11.3 16-bit timer 11.3.1 introduction the timer consists of a 16-bit free-running counter driven by a programmable prescaler. it may be used for a variety of purposes, including pulse length measurement of up to two input signals ( input capture ) or generation of up to two output waveforms ( output compare and pwm ). pulse lengths and waveform periods can be modulated from a few microseconds to several milliseconds using the timer prescaler and the cpu clock prescaler. some devices of the st7 family have two on-chip 16-bit timers. they are completely independent, and do not share any resources. they are synchronized after a device reset as long as the timer clock frequencies are not modified. this description covers one or two 16-bit timers. in the devices with two timers, register names are prefixed with ta (timer a) or tb (timer b). 11.3.2 main features programmable prescaler: f cpu divided by 2, 4 or 8. overflow status flag and maskable interrupt external clock input (must be at least 4 times slower than the cpu clock speed) with the choice of active edge output compare functions with ? 2 dedicated 16-bit registers ? 2 dedicated programmable signals ? 2 dedicated status flags ? 1 dedicated maskable interrupt input capture functions with ? 2 dedicated 16-bit registers ? 2 dedicated active edge selection signals ? 2 dedicated status flags ? 1 dedicated maskable interrupt pulse width modulation mode (pwm) one-pulse mode reduced-power mode 5 alternate functions on i/o ports (icap1, icap2, ocmp1, ocmp2, extclk). see note below. the block diagram is shown in figure 42 . note: some timer pins may not available (not bonded) in some devices. refer to the device pin out description. when reading an input signa l on a non-bonded pi n, the value will always be ?1?.
on-chip peripherals st72344xx st72345xx 94/247 doc id 12321 rev 5 11.3.3 functional description counter the main block of the programmable timer is a 16-bit free running upcounter and its associated 16-bit registers. the 16-bit registers are made up of two 8-bit registers called high & low. counter regi ster (cr): counter high register (chr) is the most significant byte (ms byte). counter low register (clr) is the least significant byte (ls byte). alternate counter register (acr) alternate counter high register (achr) is the most significant byte (ms byte). alternate counter low register (aclr) is the least significant byte (ls byte). these two read-only 16-bit registers contain the same value but with the difference that reading the aclr register does not clear the tof bit (timer overflow flag), located in the status register, (sr), (see note at the end of paragraph titled 16-bit read sequence). writing in the clr register or aclr register resets the free running counter to the fffch value. both counters have a reset value of fffch (this is the only value which is reloaded in the 16-bit timer). the reset value of both counte rs is also fffch in one-pulse mode and pwm mode. the timer clock depends on the clock control bi ts of the cr2 register, as illustrated in table 50: clock control bits on page 110 . the value in the counter register repeats every 131 072, 262 144 or 524 288 cpu clock cycles depending on the cc[1:0] bits. the timer frequency can be f cpu /2, f cpu /4, f cpu /8 or an external frequency.
st72344xx st72345xx on-chip peripherals doc id 12321 rev 5 95/247 figure 42. timer block diagram 1. if ic, oc and to interrupt requests have separate vect ors then the last or is not present (see device interrupt vector table). 16-bit timer peripheral interface counter alternate output compare register output compare edge detect overflow detect circuit 1/2 1/4 1/8 8-bit buffer internal bus latch1 ocmp1 icap1 extclk f cpu timer interrupt icf2 icf1 timd 0 0 ocf2 ocf1 tof pwm oc1e exedg iedg2 cc0 cc1 oc2e opm folv2 icie olvl1 iedg1 olvl2 folv1 ocie toie icap2 latch2 ocmp2 8 8 8 low 16 8 high 16 16 16 16 (control register 1) cr1 (control register 2) cr2 (control/status register) 6 16 8 8 8 8 8 8 high low high high high low low low exedg timer internal bus circuit1 edge detect circuit2 circuit 1 output compare register 2 input capture register 1 input capture register 2 cc[1:0] counter pin pin pin pin pin register register (see note 1) csr
on-chip peripherals st72344xx st72345xx 96/247 doc id 12321 rev 5 figure 43. 16-bit read sequence (from either the counter register or the alternate counter register) the user must read the ms byte first, then the ls byte value is buffered automatically. this buffered value remains unchanged until the 16-bit read sequence is completed, even if the user reads the ms byte several times. after a complete reading sequence, if only the clr register or aclr register are read, they return the ls byte of the count value at the time of the read. whatever the timer mode used (input capture, output compare, one-pulse mode or pwm mode) an overflow occurs when the counter rolls over from ffffh to 0000h then: the tof bit of the sr register is set. a timer interrupt is generated if: ? toie bit of the cr1 register is set and ? i bit of the cc register is cleared. if one of these conditions is false, the interr upt remains pending to be issued as soon as they are both true. clearing the overflow interrupt request is done in two steps: 1. reading the sr register while the tof bit is set. 2. an access (read or write) to the clr register. note: the tof bit is not cleared by accesses to aclr register. the advantage of accessing the aclr register rather than the clr register is that it allows simultaneous use of the overflow function and reading the free running counter at random times (for example, to measure elapsed time) without the risk of clearing the tof bit erroneously. the timer is not affected by wait mode. in halt mode, the counter stops counting until the mode is exited. counting then resumes from the previous count (device awakened by an interrupt) or from the reset count (device awakened by a reset). external clock the external clock (where available) is sele cted if cc0=1 and cc1 =1 in cr2 register. the status of the exedg bit in the cr2 register determines the type of level transition on the external clock pin extclk that will trigger the free running counter. the counter is synchronised with the falling edge of the internal cpu clock. is buffered read at t0 read returns the buffered ls byte value at t0 at t0 + t other instructions beginning of the sequence sequence completed ls byte ls byte ms byte
st72344xx st72345xx on-chip peripherals doc id 12321 rev 5 97/247 a minimum of four falling edges of the cpu clock must occur betw een two consecutive active edges of the external clock; thus the external clock frequency must be less than a quarter of the cpu clock frequency. figure 44. counter timing diagram, internal clock divided by 2 figure 45. counter timing diagram, internal clock divided by 4 figure 46. counter timing diagram, internal clock divided by 8 note: the device is in reset state when the internal reset signal is high, when it is low the device is running. cpu clock fffd fffe ffff 0000 0001 0002 0003 internal reset timer clock counter register timer overflow flag (tof) fffc fffd 0000 0001 cpu clock internal reset timer clock counter register timer overflow flag (tof) cpu clock internal reset timer clock counter register timer overflow flag (tof) fffc fffd 0000
on-chip peripherals st72344xx st72345xx 98/247 doc id 12321 rev 5 input capture in this section, the index, i , may be 1 or 2 because there are 2 input capture functions in the 16-bit timer. the two input-capture 16-bit registers (ic1r and ic2r) are used to latch the value of the free-running counter after a transition detected by the icap i pin. ic i r register is a read-only register. the active transition is software-programmable through the iedg i bit of control registers (cr i ). the timing resolution is one count of the free-running counter: ( f cpu / cc[1:0]). procedure: to use the input capture function, select the following in the cr2 register: select the timer clock (cc[1:0]) (see table 50: clock control bits on page 110 ). select the edge of the active transition on the icap2 pin with the iedg2 bit (the icap2 pin must be configured as floating input). and select the following in the cr1 register: set the icie bit to generate an interrupt after an input capture coming from either the icap1 pin or the icap2 pin select the edge of the active transition on the icap1 pin with the iedg1 bit (the icap1pin must be configured as floating input). when an input capture occurs: icf i bit is set. the ic i r register contains the value of the free running counter on the active transition on the icap i pin (see figure 48 ). a timer interrupt is generated if the icie bit is set and the i bit is cleared in the cc register. otherwise, the interrupt remains pending until both conditions become true. clearing the input capture interrupt request (i.e. clearing the icf i bit) is done in two steps: 1. reading the sr register while the icf i bit is set. 2. an access (read or write) to the ic i lr register. note: 1 after reading the icihr regist er, transfer of input capture data is inhibited and icfi will never be set until the icilr re gister is also read. 2 the icir register contains the free running counter value which corresponds to the most recent input capture. 3 the 2 input capture functions can be used together even if the timer also uses the 2 output compare functions. 4 in one-pulse mode and pwm mode only the input capture 2 can be used. 5 the alternate inputs (icap1 & icap2) are always directly connected to the timer. so any transitions on these pins activate the input capture function. table 45. ic i r register ms byte ls byte icir ic i hr ic i lr
st72344xx st72345xx on-chip peripherals doc id 12321 rev 5 99/247 moreover if one of the icapi pin is configured as an input and the second one as an output, an interrupt can be generated if the user toggle the output pin and if the icie bit is set. this can be avoided if the input capture function i is disabled by reading the icihr (see note 1). 6 the tof bit can be used with interrupt in order to measure event that go beyond the timer range (ffffh). figure 47. input capture block diagram figure 48. input capture timing diagram 1. the active edge is the rising edge. 2. the time between an event on the icapi pin and the appearance of the corresponding flag is from 2 to 3 cpu clock cycles. this depends on the moment when the icap event happens relative to the timer clock. output compare in this section, the index, i , may be 1 or 2 because there are 2 output compare functions in the 16-bit timer. this function can be used to control an output waveform or indicate when a period of time has elapsed. icie cc0 cc1 16-bit free running counter iedg1 (control register 1) cr1 (control register 2) cr2 icf2 icf1 0 0 0 (status register) sr iedg2 icap1 icap2 edge detect circuit2 16-bit ic1r register ic2r register edge detect circuit1 pin pin ff01 ff02 ff03 ff03 timer clock counter register icapi pin icapi flag icapi register
on-chip peripherals st72344xx st72345xx 100/247 doc id 12321 rev 5 when a match is found between the output compare register and the free running counter, the output compare function: assigns pins with a programmable value if the ocie bit is set sets a flag in the status register generates an interrupt if enabled two 16-bit registers output compare register 1 (oc1r) and output compare register 2 (oc2r) contain the value to be compared to the counter register each timer clock cycle. these registers are readable and writable and are not affected by the timer hardware. a reset event changes the oc i r value to 8000h. the timing resolution is one count of the free running counter: ( f cpu/ cc[1:0] ). procedure: to use the output compare function, select the following in the cr2 register: set the oc i e bit if an output is needed then the ocmp i pin is dedicated to the output compare i signal. select the timer clock (cc[1:0]) (see ta bl e 5 0 ). and select the following in the cr1 register: select the olvl i bit to applied to the ocmp i pins after the match occurs. set the ocie bit to generate an interrupt if it is needed. when a match is found between ocri register and cr register: ocf i bit is set. the ocmp i pin takes olvl i bit value (ocmp i pin latch is forced low during reset). a timer interrupt is generated if the ocie bit is set in the cr2 register and the i bit is cleared in the cc register (cc). the oc i r register value required for a specific timing application can be calculated using the following formula: where: t = output compare period (in seconds) f cpu = cpu clock frequency (in hertz) presc = timer prescaler factor (2, 4 or 8 depending on cc[1:0] bits, see ta bl e 5 0 : clock control bits ) if the timer clock is an external clock, the formula is: table 46. oc i r register ms byte ls byte oc i roc i hr oc i lr oc i r = t * f cpu presc oc i r = t * f ext
st72344xx st72345xx on-chip peripherals doc id 12321 rev 5 101/247 where: t = output compare period (in seconds) f ext = external timer clock frequency (in hertz) clearing the output compare interrupt request (i.e. clearing the ocf i bit) is done by: 1. reading the sr register while the ocf i bit is set. 2. an access (read or write) to the oc i lr register. the following procedure is recommended to prevent the ocf i bit from being set between the time it is read and the write to the oc i r register: write to the oc i hr register (further compares are inhibited). read the sr register (first step of the clearance of the ocf i bit, which may be already set). write to the oc i lr register (enables the output compare function and clears the ocf i bit). note: 1 after a processor write cycle to the ocihr r egister, the output compar e function is inhibited until the ocilr register is also written. 2 if the ocie bit is not set, the ocmpi pin is a general i/o port and the olvli bit will not appear when a match is found but an interrupt could be generated if the ocie bit is set. 3 in both internal and external clock modes, ocfi and ocmpi are set while the counter value equals the ocir register value (see figure 50 on page 102 and figure 51 on page 102 ). this behavior is the same in opm or pwm mode. 4 the output compare functions can be used both for generating external events on the ocmpi pins even if the input capture mode is also used. 5 the value in the 16-bit oc i r register and the olvi bit should be changed after each successful comparison in order to control an output waveform or establish a new elapsed timeout. forced compare output capability when the folv i bit is set by software, the olvl i bit is copied to the ocmp i pin. the olv i bit has to be toggled in order to toggle the ocmp i pin when it is enabled (oc i e bit=1). the ocf i bit is then not set by hardware, and thus no interrupt request is generated. folvl i bits have no effect in both one-pulse mode and pwm mode.
on-chip peripherals st72344xx st72345xx 102/247 doc id 12321 rev 5 figure 49. output compare block diagram figure 50. output compare timing diagram, f timer = f cpu /2 figure 51. output compare timing diagram, f timer = f cpu /4 output compare 16-bit circuit oc1r register 16 bit free running counter oc1e cc0 cc1 oc2e olvl1 olvl2 ocie (control register 1) cr1 (control register 2) cr2 0 0 0 ocf2 ocf1 (status register) sr 16-bit 16-bit ocmp1 ocmp2 latch 1 latch 2 oc2r register pin pin folv2 folv1 internal cpu clock timer clock counter register output compare register i (ocr i ) output compare flag i (ocf i ) ocmp i pin (olvl i =1) 2ed3 2ed0 2ed1 2ed2 2ed3 2ed4 2ecf internal cpu clock timer clock counter register output compare register i (ocr i ) compare register i latch 2ed3 2ed0 2ed1 2ed2 2ed3 2ed4 2ecf ocmp i pin (olvl i =1) output compare flag i (ocf i )
st72344xx st72345xx on-chip peripherals doc id 12321 rev 5 103/247 one-pulse mode one-pulse mode enables the generation of a pulse when an external event occurs. this mode is selected via the opm bit in the cr2 register. the one-pulse mode uses the input capture1 function and the output compare1 function. procedure: to use one-pulse mode: 1. load the oc1r register with the value corresponding to the length of the pulse (see the formula in the opposite column). 2. select the following in the cr1 register: ? using the olvl1 bit, select the level to be applied to the ocmp1 pin after the pulse. ? using the olvl2 bit, select the level to be applied to the ocmp1 pin during the pulse. ? select the edge of the active transition on the icap1 pin with the iedg1 bit (the icap1 pin must be configured as floating input). 3. select the following in the cr2 register: ? set the oc1e bit, the ocmp1 pin is then dedicated to the output compare 1 function. ? set the opm bit. ? select the timer clock cc[1:0] (see table 50: clock control bits on page 110 ). figure 52. one-pulse mode cycle when a valid event occurs on the icap1 pin, the counter value is loaded in the icr1 register. the counter is then initialized to fffch, the olvl2 bit is output on the ocmp1 pin and the icf1 bit is set. because the icf1 bit is set when an active edge occurs, an interrupt can be generated if the icie bit is set. clearing the input capture interrupt request (i.e. clearing the icf i bit) is done in two steps: 1. reading the sr register while the icf i bit is set. 2. an access (read or write) to the ic i lr register. event occurs counter = oc1r ocmp1 = olvl1 when when on icap1 one-pulse mode cycle ocmp1 = olvl2 counter is reset to fffch icf1 bit is set icr1 = counter
on-chip peripherals st72344xx st72345xx 104/247 doc id 12321 rev 5 the oc1r register value required for a specif ic timing application can be calculated using the following formula: where: t = pulse period (in seconds) f cpu = cpu clock frequency (in hertz) presc = timer prescaler factor (2, 4 or 8 depending on the cc[1:0] bits, see ta b l e 5 0 : clock control bits ) if the timer clock is an external clock the formula is: where: t = pulse period (in seconds) f ext = external timer clock frequency (in hertz) when the value of the counter is equal to the value of the contents of the oc1r register, the olvl1 bit is output on the ocmp1 pin (see figure 53 ). note: 1 the ocf1 bit cannot be set by hardware in one-pulse mode but the ocf2 bit can generate an output compare interrupt. 2 when the pulse width modulation (pwm) and one-pulse mode (opm) bits are both set, the pwm mode is the only active one. 3 if olvl1=olvl2 a continuous signal will be seen on the ocmp1 pin. 4 the icap1 pin can not be used to perform input capture. the icap2 pin can be used to perform input capture (icf2 can be set and ic2r can be loaded) but the user must take care that the counter is reset each time a valid edge occurs on the icap1 pin and icf1 can also generates interrupt if icie is set. 5 when one-pulse mode is used oc1r is dedica ted to this mode. nevertheless oc2r and ocf2 can be used to indicate a period of time has been elapsed but cannot generate an output waveform because the level olvl2 is dedicated to the one-pulse mode. figure 53. one-pulse mode timing example 1. iedg1=1, oc1r=2ed0h, olvl1=0, olvl2=1. oc i r value = t * f cpu presc - 5 oc i r = t * f ext -5 counter fffc fffd fffe 2ed0 2ed1 2ed2 2ed3 fffc fffd olvl2 olvl2 olvl1 icap1 ocmp1 compare1 01f8 01f8 2ed3 ic1r
st72344xx st72345xx on-chip peripherals doc id 12321 rev 5 105/247 figure 54. pulse width modu lation mode timing example 1. oc1r = 2ed0h, oc2r = 34e2, olvl1 = 0, olvl2 = 1 pulse-width modulation mode pulse-width modulation (pwm) mode enables the generation of a signal with a frequency and pulse length determined by the value of the oc1r and oc2r registers. pulse-width modulation mode uses the complete output compare 1 function plus the oc2r register, and so this functionality can no t be used when pwm mode is activated. in pwm mode, double buffering is implemented on the output compare registers. any new values written in the oc1r and oc2r registers are loaded in their respective shadow registers (double buffer) only at the end of the pwm period (oc2) to avoid spikes on the pwm output pin (ocmp1). the shadow registers contain the reference values for comparison in pwm ?double buffering? mode. note: there is a locking mechanism for transferring the ocir value to the buffer. after a write to the ocihr register, transfer of the new compare value to the buffer is inhibited until ocilr is also written. unlike in output compare mode, the compare function is always enabled in pwm mode. procedure: to use pulse-width modulation mode: 1. load the oc2r register with the value corresponding to the period of the signal using the formula in the opposite column. 2. load the oc1r register with the value corresponding to the period of the pulse if (olvl1=0 and olvl2=1) using the formula in the opposite column. 3. select the following in the cr1 register: ? using the olvl1 bit, select the level to be applied to the ocmp1 pin after a successful comparison with oc1r register. ? using the olvl2 bit, select the level to be applied to the ocmp1 pin after a successful comparison with oc2r register. 4. select the following in the cr2 register: ? set oc1e bit: the ocmp1 pin is then dedicated to the output compare 1 function. ? set the pwm bit. ? select the timer clock (cc[1:0]) (see table 50: clock control bits ). counter 34e2 34e2 fffc olvl2 olvl2 olvl1 ocmp1 compare2 compare1 compare2 fffc fffd fffe 2ed0 2ed1 2ed2
on-chip peripherals st72344xx st72345xx 106/247 doc id 12321 rev 5 figure 55. pulse width modulation cycle if olvl1=1 and olvl2=0 the length of the positive pulse is the difference between the oc2r and oc1r registers. if olvl1=olvl2 a continuous signal will be seen on the ocmp1 pin. the oc i r register value required for a specific timing application can be calculated using the following formula: where: t = signal or pulse period (in seconds) f cpu = cpu clock frequency (in hertz) presc = timer prescaler factor (2, 4 or 8 depending on cc[1:0] bits, see ta bl e 5 0 : clock control bits ) if the timer clock is an external clock the formula is: where: t = signal or pulse period (in seconds) f ext = external timer clock frequency (in hertz) the output compare 2 event causes the counter to be initialized to fffch (see figure 54 ) note: 1 the ocf1 and ocf2 bits cannot be set by hardware in pwm mode therefore the output compare interrupt is inhibited. 2 the icf1 bit is set by hardware when the c ounter reaches the oc2r value and can produce a timer interrupt if the icie bit is set and the i bit is cleared. 3 in pwm mode the icap1 pin can not be used to perform input capture because it is disconnected to the timer. the icap2 pin can be used to perform input capture (icf2 can be set and ic2r can be loaded) but the user must take care that the counter is reset each period and icf1 can also generate interrupt if icie is set. 4 when the pulse-width modulation (pwm) and one-pulse mode (opm) bits are both set, the pwm mode is the only active one. counter ocmp1 = olvl2 counter = oc2r ocmp1 = olvl1 when when = oc1r pulse-width modulation cycle counter is reset to fffch icf1 bit is set oc i r value = t * f cpu presc - 5 oc i r = t * f ext -5
st72344xx st72345xx on-chip peripherals doc id 12321 rev 5 107/247 11.3.4 low-power modes 11.3.5 interrupts note: the 16-bit timer interrupt events are connected to the same interrupt vector (see interrupts chapter). these events generate an interrupt if the corresponding enable control bit is set and the interrupt mask in the cc regi ster is reset (r im instruction). table 47. low-power mode description mode description wait no effect on 16-bit timer. timer interrupts cause the devi ce to exit from wait mode. halt 16-bit timer registers are frozen. in halt mode, the counter stops counting unt il halt mode is exited. counting resumes from the previous count when the device is woken up by an interrupt with ?exit from halt mode? capability or from the counter reset value when the device is woken up by a reset. if an input capture event occurs on the icap i pin, the input capture detection circuitry is armed. consequently, when the device is woken up by an interrupt with ?exit from halt mode? capability, the icf i bit is set, and the counter value present when exiting from halt mode is captured into the ic i r register. table 48. interrupt events interrupt event event flag enable control bit exit from wait exit from halt input capture 1 event/counter reset in pwm mode icf1 icie ye s n o input capture 2 event icf2 yes no output compare 1 event (not available in pwm mode) ocf1 ocie ye s n o output compare 2 event (not available in pwm mode) ocf2 yes no timer overflow event tof toie yes no
on-chip peripherals st72344xx st72345xx 108/247 doc id 12321 rev 5 11.3.6 summary of timer modes 11.3.7 register description each timer is associated with three control and status registers, and with six pairs of data registers (16-bit values) relating to the two input captures, the two output compares, the counter and the alternate counter. control register 1 (cr1) read/write reset value: 0000 0000 (00h) bit 7 = icie input capture interrupt enable. 0: interrupt is inhibited. 1: a timer interrupt is generated whenever the icf1 or icf2 bit of the sr register is set. bit 6 = ocie output compare interrupt enable. 0: interrupt is inhibited. 1: a timer interrupt is generated whenever the ocf1 or ocf2 bit of the sr register is set. bit 5 = toie timer overflow interrupt enable. 0: interrupt is inhibited. 1: a timer interrupt is enabled whenever the tof bit of the sr register is set. bit 4 = folv2 forced output compare 2. this bit is set and cleared by software. 0: no effect on the ocmp2 pin. 1:forces the olvl2 bit to be copied to the ocmp2 pin, if the oc2e bit is set and even if there is no su ccessful comparison. table 49. timer modes modes available resources input capture 1 input capture 2 output compare 1 output compare 2 input capture (1 and/or 2) yes yes yes yes output compare (1 and/or 2) yes yes yes yes one-pulse mode no not recommended (1) no partially (2) pwm mode no not recommended (3) no no 1. see note 4 in one-pulse mode on page 103 2. see note 5 in one-pulse mode on page 103 3. see note 4 in : pulse-width modulation mode on page 105 7 0 icie ocie toie folv2 folv1 olvl2 iedg1 olvl1 read/write
st72344xx st72345xx on-chip peripherals doc id 12321 rev 5 109/247 bit 3 = folv1 forced output compare 1. this bit is set and cleared by software. 0: no effect on the ocmp1 pin. 1: forces olvl1 to be copied to the ocmp1 pin, if the oc1e bit is set and even if there is no successful comparison. bit 2 = olvl2 output level 2. this bit is copied to the ocmp2 pin whenever a successful comparison occurs with the oc2r register and ocxe is set in the cr2 re gister. this value is copied to the ocmp1 pin in one-pulse mode and pulse-width modulation mode. bit 1 = iedg1 input edge 1. this bit determines which type of level tr ansition on the icap1 pin will trigger the capture. 0: a falling edge triggers the capture. 1: a rising edge triggers the capture. bit 0 = olvl1 output level 1. the olvl1 bit is copied to the ocmp1 pin whenever a successful comparison occurs with the oc1r register and the oc1e bit is set in the cr2 register. control register 2 (cr2) reset value: 0000 0000 (00h) bit 7 = oc1e output compare 1 pin enable. this bit is used only to output the signal from the timer on the ocmp1 pin (olv1 in output compare mode, both olv1 and olv2 in pwm and one-pulse mode). whatever the value of the oc1e bit, the output compare 1 function of the timer remains active. 0: ocmp1 pin alternate function disabled (i/o pin free for general-purpose i/o). 1: ocmp1 pin alternate function enabled. bit 6 = oc2e output compare 2 pin enable. this bit is used only to output the signal from the timer on the ocmp2 pin (olv2 in output compare mode). whatever the value of the oc2e bit, the output compare 2 function of the timer remains active. 0: ocmp2 pin alternate function disabled (i/o pin free for general-purpose i/o). 1: ocmp2 pin alternate function enabled. bit 5 = opm one-pulse mode. 0: one-pulse mode is not active. 1: one-pulse mode is active, the icap1 pin can be used to trigger one pulse on the ocmp1 pin; the active transition is given by the iedg1 bit. the length of the generated pulse depends on the contents of the oc1r register. bit 4 = pwm pulse-width modulation. 0: pwm mode is not active. 1: pwm mode is active, the ocmp1 pin out puts a programmable cyclic signal; the 7 0 oc1e oc2e opm pwm cc1 cc0 iedg2 exedg read/write
on-chip peripherals st72344xx st72345xx 110/247 doc id 12321 rev 5 length of the pulse depends on the value of oc1r register; the period depends on the value of oc2r register. bits 3:2 = cc[1:0] clock control. the timer clock mode depends on these bits: note: if the external clock pin is not available, programming the external clock configuration stops the counter. bit 1 = iedg2 input edge 2. this bit determines which type of level tr ansition on the icap2 pin will trigger the capture. 0: a falling edge triggers the capture. 1: a rising edge triggers the capture. bit 0 = exedg external clock edge. this bit determines which type of level tran sition on the external clock pin extclk will trigger the counter register. 0: a falling edge triggers the counter register. 1: a rising edge triggers the counter register. control/status register (csr) reset value: 0000 0000 (00h) the three least significant bits are not used. bit 7 = icf1 input capture flag 1. 0: no input capture (reset value). 1: an input capture has occurred on the icap1 pin or the counter has reached the oc2r value in pwm mode. to clear this bit, first read the sr register, then read or write the low byte of the ic1r (ic1lr) register. bit 6 = ocf1 output compare flag 1. 0: no match (reset value). 1: the content of the free running counter has matched the content of the oc1r register. to clear this bit, first read the sr register, then read or write the low byte of the oc1r (oc1lr) register. table 50. clock control bits timer clock cc1 cc0 f cpu / 4 0 0 f cpu / 2 0 1 f cpu / 8 1 0 external clock (where available) 1 1 7 0 icf1 ocf1 tof icf2 ocf2 timd 0 0 read-only
st72344xx st72345xx on-chip peripherals doc id 12321 rev 5 111/247 bit 5 = tof timer overflow flag. 0: no timer overflow (reset value). 1: the free running counter rolled over from ffffh to 0000h. to clear this bit, first read the sr register, then read or write the low byte of the cr (clr) register. note: reading or writing the aclr register does not clear tof. bit 4 = icf2 input capture flag 2. 0: no input capture (reset value). 1: an input capture has occurred on the icap2 pin. to clear this bit, first read the sr register, then read or write the low byte of the ic2r (ic2lr) register. bit 3 = ocf2 output compare flag 2. 0: no match (reset value). 1: the content of the free running counter has matched the content of the oc2r register. to clear this bit, first read the sr register, then read or write the low byte of the oc2r (oc2lr) register. bit 2 = timd timer disable. this bit is set and cleared by software. when set, it freezes the timer prescaler and counter and disabled the output functions (ocmp1 and ocmp2 pins) to reduce power consumption. access to th e timer registers is still av ailable, allowing the timer configuration to be chan ged while it is disabled. 0: timer enabled 1: timer prescaler, counter and outputs disabled bits 1:0 = reserved, must be kept cleared. input capture 1 high register (ic1hr) reset value: undefined this is an 8-bit read-only register that contains the high part of the counter value (transferred by the input capture 1 event). input capture 1 low register (ic1lr) reset value: undefined this is an 8-bit read only register that contains the low part of the counter value (transferred by the input capture 1 event). 7 0 msb lsb read only 7 0 msb lsb read only
on-chip peripherals st72344xx st72345xx 112/247 doc id 12321 rev 5 output compare 1 high register (oc1hr) read/write reset value: 1000 0000 (80h) this is an 8-bit register that contains the high part of the value to be compared to the chr register. output compare 1 low register (oc1lr) reset value: 0000 0000 (00h) this is an 8-bit register that contains the low part of the value to be compared to the clr register. output compare 2 high register (oc2hr) reset value: 1000 0000 (80h) this is an 8-bit register that contains the high part of the value to be compared to the chr register. output compare 2 low register (oc2lr) reset value: 0000 0000 (00h) this is an 8-bit register that contains the low part of the value to be compared to the clr register. counter high register (chr) reset value: 1111 1111 (ffh) this is an 8-bit register that contains the high part of the counter value. 7 0 msb lsb read/write 7 0 msb lsb read/write 7 0 msb lsb read/write 7 0 msb lsb read/write 7 0 msb lsb read-only
st72344xx st72345xx on-chip peripherals doc id 12321 rev 5 113/247 counter low register (clr) reset value: 1111 1100 (fch) this is an 8-bit register that contains the low part of the counter value. a write to this register resets the counter. an access to this register after accessing the csr register clears the tof bit. alternate counter high register (achr) reset value: 1111 1111 (ffh) this is an 8-bit register that contains the high part of the counter value. alternate counter low register (aclr) reset value: 1111 1100 (fch) this is an 8-bit register that contains the low part of the counter value. a write to this register resets the counter. an access to this register after an access to csr register does not clear the tof bit in the csr register. input capture 2 high register (ic2hr) reset value: undefined this is an 8-bit read only register that contains the high part of the counter value (transferred by the input capture 2 event). input capture 2 low register (ic2lr) reset value: undefined this is an 8-bit read only register that contains the low part of the counter value (transferred by the input capture 2 event). 7 0 msb lsb read-only 7 0 msb lsb read-only 7 0 msb lsb read-only 7 0 msb lsb read-only 7 0 msb lsb read-only
on-chip peripherals st72344xx st72345xx 114/247 doc id 12321 rev 5 table 51. 16-bit timer register map and reset values address (hex.) register label 7654321 0 timer a: 32 timer b: 42 cr1 reset value icie 0 ocie 0 toie 0 folv2 0 folv1 0 olvl2 0 iedg1 0 olvl1 0 timer a: 31 timer b: 41 cr2 reset value oc1e 0 oc2e 0 opm 0 pwm 0 cc1 0 cc0 0 iedg2 0 exedg 0 timer a: 33 timer b: 43 csr reset value icf1 x ocf1 x tof x icf2 x ocf2 x timd 0 - x - x timer a: 34 timer b: 44 ic1hr reset value msb xxx xxxx lsb x timer a: 35 timer b: 45 ic1lr reset value msb xxx xxxx lsb x timer a: 36 timer b: 46 oc1hr reset value msb 100 0000 lsb 0 timer a: 37 timer b: 47 oc1lr reset value msb 000 0000 lsb 0 timer a: 3e timer b: 4e oc2hr reset value msb 100 0000 lsb 0 timer a: 3f timer b: 4f oc2lr reset value msb 000 0000 lsb 0 timer a: 38 timer b: 48 chr reset value msb 111 1111 lsb 1 timer a: 39 timer b: 49 clr reset value msb 111 1110 lsb 0 timer a: 3a timer b: 4a achr reset value msb 1111111 lsb 1 timer a: 3b timer b: 4b aclr reset value msb 111111 0 lsb 0 timer a: 3c timer b: 4c ic2hr reset value msb xxx xxxx lsb x timer a: 3d timer b: 4d ic2lr reset value msb xxx xxxx lsb x
st72344xx st72345xx on-chip peripherals doc id 12321 rev 5 115/247 11.4 serial peripheral interface (spi) 11.4.1 introduction the serial peripheral interface (spi) allows full-duplex, synchronous, serial communication with external devices. an spi system may consist of a master and one or more slaves or a system in which devices may be either masters or slaves. 11.4.2 main features full-duplex synchronous transfers (on three lines) simplex synchronous transfers (on two lines) master or slave operation 6 master mode frequencies (f cpu /4 max.) f cpu /2 max. slave mode frequency (see note) ss management by software or hardware programmable clock polarity and phase end-of-transfer interrupt flag write collision, master mode fault and overrun flags note: in slave mode, continuous transmission is not possible at maximum frequency due to the software overhead for clearing status flags and to initiate the next transmission sequence. 11.4.3 general description figure 56 on page 116 shows the serial peripheral interface (spi) block diagram. there are three registers: spi control register (spicr) spi control/status register (spicsr) spi data register (spidr) the spi is connected to external devices through four pins: miso: master in / slave out data mosi: master out / slave in data sck: serial clock out by spi masters and input by spi slaves ss : slave select: this input signal acts as a ?chip select? to let the spi master communicate with slaves individually and to avoid contention on the data lines. slave ss inputs can be driven by standard i/o ports on the master device.
on-chip peripherals st72344xx st72345xx 116/247 doc id 12321 rev 5 figure 56. serial peripheral interface block diagram functional description a basic example of interconnections between a single master and a single slave is illustrated in figure 57 . the mosi pins are connected together and the miso pins are connected together. in this way data is transferred serially between master and slave (most significant bit first). the communication is always initiated by th e master. when the master device transmits data to a slave device via mosi pin, the sl ave device responds by sending data to the master device via the miso pin. this implies full duplex communication with both data out and data in synchronized with the same clock signal (which is provided by the master device via the sck pin). to use a single data line, the miso and mosi pins must be connected at each node (in this case only simplex communication is possible). four possible data/clock timing relationships may be chosen (see figure 60 on page 121 ) but master and slave must be programmed with the same timing mode. spidr read buffer 8-bit shift register write read data/address bus spi spie spe mstr cpha spr0 spr1 cpol serial clock generator mosi miso ss sck control state spicr spicsr interrupt request master control spr2 0 7 0 7 spif wcol modf 0 ovr ssi ssm sod sod bit ss 1 0
st72344xx st72345xx on-chip peripherals doc id 12321 rev 5 117/247 figure 57. single master/ single slave application slave select management as an alternative to using the ss pin to control the slave select signal, the application can choose to manage the slave select signal by software. this is configured by the ssm bit in the spicsr register (see figure 59 ). in software management, the external ss pin is free for other application uses and the internal ss signal level is driven by writing to the ssi bit in the spicsr register. in master mode: ?ss internal must be held high continuously in slave mode: there are two cases depending on the data/clock timing relationship (see figure 58 ): if cpha = 1 (data latched on second clock edge): ?ss internal must be held low during the entire transmission. this implies that in single slave applications the ss pin either can be tied to v ss , or made free for standard i/o by managing the ss function by software (ssm = 1 and ssi = 0 in the in the spicsr register) if cpha = 0 (data latched on first clock edge): ?ss internal must be held low during byte transmission and pulled high between each byte to allow the slave to write to the shift register. if ss is not pulled high, a write collision error will occur when the sl ave writes to the shift register (see write collision error (wcol) on page 122 ). 8-bit shift register spi clock generator 8-bit shift register miso mosi mosi miso sck sck slave master ss ss +5v msbit lsbit msbit lsbit not used if ss is managed by software
on-chip peripherals st72344xx st72345xx 118/247 doc id 12321 rev 5 figure 58. generic ss timing diagram figure 59. hardware/software slave select management master mode operation in master mode, the serial clock is output on the sck pin. the clock frequency, polarity and phase are configured by software (refer to the description of the spicsr register). note: the idle state of sck must correspond to the polarity selected in the spicsr register (by pulling up sck if cpol = 1 or pulling down sck if cpol = 0). how to operate the spi in master mode to operate the spi in master mode, perform the following steps in order: 1. write to the spicr register: ? select the clock frequency by configuring the spr[2:0] bits. ? select the clock polarity and clock phase by configuring the cpol and cpha bits. figure 60 shows the four possible configurations. note that the slave must have the same cpol and cpha settings as the master. 2. write to the spicsr register: ? either set the ssm bit and set the ssi bit or clear the ssm bit and tie the ss pin high for the complete byte transmit sequence. 3. write to the spicr register: ? set the mstr and spe bits note that the mstr and spe bi ts remain set only if ss is high). note: important: if the spicsr register is not written first, the spicr register setting (mstr bit) may be not taken into account. the transmit sequence begins when software writes a byte in the spidr register. mosi/miso master ss slave ss (if cpha = 0) byte 1 byte 2 byte 3 1 0 ss internal ssm bit ssi bit ss external pin
st72344xx st72345xx on-chip peripherals doc id 12321 rev 5 119/247 master mode transmit sequence when software writes to the spidr register, the data byte is loaded into the 8-bit shift register and then shifted out serially to the mosi pin most significant bit first. when data transfer is complete: the spif bit is set by hardware. an interrupt request is generated if the spie bit is set and the interrupt mask in the ccr register is cleared. clearing the spif bit is performed by the following software sequence: 1. an access to the spicsr register while the spif bit is set 2. a read to the spidr register note: while the spif bit is set, all writes to the spidr register are inhibited until the spicsr register is read. slave mode operation in slave mode, the serial clock is received on the sck pin from the master device. to operate the spi in slave mode: 1. write to the spicsr register to perform the following actions: ? select the clock polarity and clock phase by configuring the cpol and cpha bits (see figure 60 ). note that the slave must have the same cpol and cpha settings as the master. ? manage the ss pin as described in slave select management on page 117 and figure 58 . if cpha = 1 ss must be held low continuously. if cpha = 0 ss must be held low during byte transmission and pulled up between each byte to let the slave write in the shift register. 2. write to the spicr register to clear the mstr bit and se t the spe bit to enable the spi i/o functions. slave mode transmit sequence when software writes to the spidr register, the data byte is loaded into the 8-bit shift register and then shifted out serially to the miso pin most significant bit first. the transmit sequence begins when the slave device receives the clock signal and the most significant bit of the data on its mosi pin. when data transfer is complete: the spif bit is set by hardware. an interrupt request is generated if spie bit is set and interrupt mask in the ccr register is cleared. clearing the spif bit is performed by the following software sequence: 1. an access to the spicsr register while the spif bit is set 2. a write or a read to the spidr register
on-chip peripherals st72344xx st72345xx 120/247 doc id 12321 rev 5 note: while the spif bit is set, all writes to the spidr register are inhibited until the spicsr register is read. the spif bit can be cleared during a second transmission; however, it must be cleared before the second spif bit in order to prevent an overrun condition (see overrun condition (ovr) on page 122 ). 11.4.4 clock phase and clock polarity four possible timing relationships may be chosen by software, using the cpol and cpha bits (see figure 60 ). note: the idle state of sck must correspond to the polarity selected in the spicsr register (by pulling up sck if cpol = 1 or pulling down sck if cpol = 0). the combination of the cpol clock polarity and cpha (clock phase) bits selects the data capture clock edge. figure 60 shows an spi transfer with the four combinations of the cpha and cpol bits. the diagram may be interpreted as a master or slave timing diagram where the sck pin, the miso pin and the mosi pin are directly connected between the master and the slave device. note: if cpol is changed at the communication byte boundaries, the spi must be disabled by resetting the spe bit.
st72344xx st72345xx on-chip peripherals doc id 12321 rev 5 121/247 figure 60. data clock timing diagram 1. this figure should not be used as a replacement for parametric inform ation. refer to the electrical characterist ics chapter. 11.4.5 error flags master mode fault (modf) master mode fault occurs when the master device?s ss pin is pulled low. when a master mode fault occurs: the modf bit is set and an spi interrupt request is generated if the spie bit is set. the spe bit is reset. this blocks all output from the device and disables the spi peripheral. the mstr bit is reset, thus forcing the device into slave mode. sck msbit bit 6 bit 5 bit 4 bit3 bit 2 bit 1 lsbit msbit bit 6 bit 5 bit 4 bit3 bit 2 bit 1 lsbit miso (from master) mosi (from slave) ss (to slave) capture strobe cpha = 1 msbit bit 6 bit 5 bit 4 bit3 bit 2 bit 1 lsbit msbit bit 6 bit 5 bit 4 bit3 bit 2 bit 1 lsbit miso (from master) mosi ss (to slave) capture strobe cpha = 0 (from slave) (cpol = 1) sck (cpol = 0) sck (cpol = 1) sck (cpol = 0)
on-chip peripherals st72344xx st72345xx 122/247 doc id 12321 rev 5 clearing the modf bit is done through a software sequence: 1. a read access to the spicsr regi ster while the modf bit is set. 2. a write to the spicr register. notes: to avoid any conflicts in an application with multiple slaves, the ss pin must be pulled high during the modf bit clearing sequence. the spe and mstr bits may be restored to their original state during or after this clearing sequence. hardware does not allow the us er to set the spe and mstr bits while the modf bit is set except in the modf bit clearing sequence. in a slave device, the modf bit can not be set, but in a multimaster configuration the device can be in slave mode with the modf bit set. the modf bit indicates that there might have been a multimaster conflict and allows software to handle this using an interrupt routine and either perform a reset or return to an application default state. overrun condition (ovr) an overrun condition occurs when the master device has sent a data byte and the slave device has not cleared the spif bit issued from the previously transmitted byte. when an overrun occurs: the ovr bit is set and an interrupt request is generated if the spie bit is set. in this case, the receiver buffer contains the byte sent after the spif bit was last cleared. a read to the spidr register returns this byte. all other bytes are lost. the ovr bit is cleared by reading the spicsr register. write collision error (wcol) a write collision occurs when the software trie s to write to the spidr register while a data transfer is taking place with an external device. when this happens, the transfer continues uninterrupted and the softwa re write will be unsuccessful. write collisions can occur both in master and slave mode. see also slave select management on page 117 . note: a ?read collision? will never occur since the re ceived data byte is placed in a buffer in which access is always synchronous with the cpu operation. the wcol bit in the spicsr register is set if a write collision occurs. no spi interrupt is generated when the wcol bit is set (the wcol bit is a status flag only). clearing the wcol bit is done through a software sequence (see figure 61 ).
st72344xx st72345xx on-chip peripherals doc id 12321 rev 5 123/247 figure 61. clearing the wcol bit (write collision flag) software sequence 1. writing to the spidr register instead of reading it does not reset the wcol bit. single master and multimaster configurations there are two types of spi systems: sing le master system an d multimaster system. single master system a typical single master system may be configured using a device as the master and four devices as slaves (see figure 62 ). the master device selects the individual slav e devices by using four pins of a parallel port to control the four ss pins of the slave devices. the ss pins are pulled high during reset since the master device ports will be forced to be inputs at that time, thus disabling the slave devices. note: to prevent a bus conflict on the miso line, the master allows only one active slave device during a transmission. for more security, the slave device may respond to the master with the received data byte. then the master will receive the previous byte back from the slave device if all miso and mosi pins are connected and the slave has not written to its spidr register. other transmission security methods can use ports for handshake lines or data bytes with command fields. multimaster system a multimaster system may also be configured by the user. transfer of master control could be implemented using a handshake method through the i/o ports or by an exchange of code messages through t he serial peripheral interface system. the multimaster system is prin cipally handled by the mstr bit in the spicr register and the modf bit in the spicsr register. clearing sequence after spif = 1 (end of a data byte transfer) 1st step read spicsr read spidr 2nd step spif = 0 wcol = 0 clearing sequence before spif = 1 (during a data byte transfer) 1st step 2nd step wcol = 0 read spicsr read spidr result result
on-chip peripherals st72344xx st72345xx 124/247 doc id 12321 rev 5 figure 62. single master / multiple slave configuration 11.4.6 low-power modes using the spi to wake up the device from halt mode in slave configuration, the spi is able to wake up the device from halt mode through a spif interrupt. the data received is subsequently read from the spidr register when the software is running (interrupt vector fetch). if multiple data transfers have been performed before software clears the spif bit, then the ovr bit is set by hardware. note: when waking up from halt mode, if the spi remains in slave mode, it is recommended to perform an extra communications cycle to bring the spi from halt mode state to normal state. if the spi exits from slave mode, it returns to normal state immediately. caution: the spi can wake up the device from halt mode only if the slave select signal (external ss pin or the ssi bit in the spicsr register) is low when the device enters halt mode. so, if slave selection is configured as external (see slave select management ), make sure the master drives a low level on the ss pin when the slave enters halt mode. miso mosi mosi mosi mosi mosi miso miso miso miso ss ss ss ss ss sck sck sck sck sck 5v ports slave device slave device slave device slave device master device table 52. description mode description wait no effect on spi. spi interrupt events cause the de vice to exit from wait mode. halt spi registers are frozen. in halt mode, the spi is inactive. spi operation resumes when the device is woken up by an interrupt with ?exit from halt mode? capability. the data received is subsequently read from the spidr register when the software is ru nning (interrupt vector fetching). if several data are received before the wake-up event, then an overrun error is generated. this error can be detected after the fetch of the interrupt routine that woke up the device.
st72344xx st72345xx on-chip peripherals doc id 12321 rev 5 125/247 11.4.7 interrupts note: the spi interrupt events are connected to the same interrupt vector (see interrupts chapter). they generate an interrupt if the corresponding enable control bit is set and the interrupt mask in the cc register is reset (rim instruction). 11.4.8 register description spi control register (spicr) reset value: 0000 xxxx (0xh) bit 7 = spie serial peripheral interrupt enable this bit is set and cleared by software. 0: interrupt is inhibited 1: an spi interrupt is generated whenever an end of transfer event, master mode fault or overrun error occurs (spif = 1, modf = 1 or ovr = 1 in the spicsr register) bit 6 = spe serial peripheral output enable this bit is set and cleared by software. it is also cleared by hardware when, in master mode, ss =0 (see master mode fault (modf) on page 121 ). the spe bit is cleared by reset, so the spi peripheral is not initially connected to the external pins. 0: i/o pins free for general purpose i/o 1: spi i/o pin alternate functions enabled bit 5 = spr2 divider enable this bit is set and cleared by software and is cleared by reset. it is used with the spr[1:0] bits to set the baud rate. refer to table 54: spi master mode sck frequency . 0: divider by 2 enabled 1: divider by 2 disabled note: this bit has no effect in slave mode. table 53. interrupt events interrupt event event flag enable control bit exit from wait exit from halt spi end of transfer event spif spie yes ye s master mode fault event modf no overrun error ovr 7 0 spie spe spr2 mstr cpol cpha spr1 spr0 read/write
on-chip peripherals st72344xx st72345xx 126/247 doc id 12321 rev 5 bit 4 = mstr master mode this bit is set and cleared by software. it is also cleared by hardware when, in master mode, ss =0 (see master mode fault (modf) on page 121 ). 0: slave mode 1: master mode. the function of the sck pin changes from an input to an output and the functions of the miso and mosi pins are reversed. bit 3 = cpol clock polarity this bit is set and cleared by software. this bit determines the idle state of the serial clock. the cpol bit affects both the master and slave modes. 0: sck pin has a low level idle state 1: sck pin has a high level idle state note: if cpol is changed at the communication byte boundaries, the spi must be disabled by resetting the spe bit. bit 2 = cpha clock phase this bit is set and cleared by software. 0: the first clock transition is the first data capture edge. 1: the second clock transition is the first capture edge. note: the slave must have the same cpol and cpha settings as the master. bits 1:0 = spr[1:0] serial clock frequency these bits are set and cleared by software. used with the spr2 bit, they select the baud rate of the spi serial clock sck output by the spi in master mode. note: these 2 bits have no effect in slave mode. spi control/status register (spicsr) reset value: 0000 0000 (00h) table 54. spi master mode sck frequency serial clock spr2 spr1 spr0 f cpu /4 1 0 0 f cpu /8 0 f cpu /16 1 f cpu /32 1 1 0 f cpu /64 0 f cpu /128 1 7 0 spif wcol ovr modf - sod ssm ssi read-only reserved read/write
st72344xx st72345xx on-chip peripherals doc id 12321 rev 5 127/247 bit 7 = spif serial peripheral data transfer flag (read-only) this bit is set by hardware when a transfer has been completed. an interrupt is generated if spie = 1 in the spicr register. it is cleared by a software sequence (an access to the spicsr register followed by a write or a read to the spidr register). 0: data transfer is in progress or the flag has been cleared. 1: data transfer between the device and an external device has been completed. note: while the spif bit is set, all writes to the spidr register are inhibited until the spicsr register is read. bit 6 = wcol write collision status (read-only) this bit is set by hardware when a write to the spidr register is done during a transmit sequence. it is cleared by a software sequence (see figure 61 ). 0: no write collision occurred 1: a write collision has been detected bit 5 = ovr s pi overrun error (read-only) this bit is set by hardware when the byte currently being received in the shift register is ready to be transferred into the spidr register while spif = 1 (see overrun condition (ovr) ). an interrupt is generated if spie = 1 in the spicr register. the ovr bit is cleared by software reading the spicsr register. 0: no overrun error 1: overrun error detected bit 4 = modf mode fault flag (read-only) this bit is set by hardware when the ss pin is pulled low in master mode (see master mode fault (modf) on page 121 ). an spi interrupt can be generated if spie = 1 in the spicr register. this bit is cleared by a software sequence (an access to the spicsr register while modf = 1 followed by a write to the spicr register). 0: no master mode fault detected 1: a fault in master mode has been detected bit 3 = reserved, must be kept cleared. bit 2 = sod spi output disable this bit is set and cleared by software. when set, it disables the alternate function of the spi output (mosi in master mode / miso in slave mode) 0: spi output enabled (if spe = 1) 1: spi output disabled bit 1 = ssm ss management this bit is set and cleared by software. when set, it disables the alternate function of the spi ss pin and uses the ssi bit value instead. see slave select management on page 117 . 0: hardware management (ss managed by external pin) 1: software management (internal ss signal controlled by ssi bit. external ss pin free for general-purpose i/o) bit 0 = ssi ss internal mode this bit is set and cleared by software. it acts as a ?chip select? by controlling the level of the ss slave select signal when the ssm bit is set. 0: slave selected 1: slave deselected
on-chip peripherals st72344xx st72345xx 128/247 doc id 12321 rev 5 spi data i/o register (spidr) reset value: undefined the spidr register is used to transmit and receive data on the serial bus. in a master device, a write to this regi ster will initiate transmission/ reception of another byte. note: during the last clock cycle the spif bit is set, a copy of the received data byte in the shift register is moved to a buffer. when the user reads the serial peripheral data i/o register, the buffer is actually being read. while the spif bit is set, all writes to the spidr register are inhibited until the spicsr register is read. warning: a write to the spidr register places data directly into the shift register for transmission. a read to the spidr register returns the value located in the buffer and not the content of the shift register (see figure 56 ). 7 0 d7 d6 d5 d4 d3 d2 d1 d0 read/write table 55. spi register map and reset values address (hex.) register label 76543210 0021h spidr reset value msb xxx xxxx lsb x 0022h spicr reset value spie 0 spe 0 spr2 0 mstr 0 cpol x cpha x spr1 x spr0 x 0023h spicsr reset value spif 0 wcol 0 or 0 modf 00 sod 0 ssm 0 ssi 0
st72344xx st72345xx on-chip peripherals doc id 12321 rev 5 129/247 11.5 sci serial comm unication interface 11.5.1 introduction the serial communications interface (sci) offers a flexible means of full-duplex data exchange with external equipment requiring an industry standard nrz asynchronous serial data format. the sci offers a very wide range of baud rates using two baud rate generator systems. 11.5.2 main features full-duplex, asynchronous communications nrz standard format (mark/space) dual baud rate generator systems independently programmable transmit and receive baud rates up to 500k baud programmable data word length (8 or 9 bits) receive buffer full, transmit buffer empty and end of transmission flags 2 receiver wake-up modes: ? address bit (msb) ? idle line muting function for multiprocessor configurations separate enable bits for transmitter and receiver 4 error detection flags: ? overrun error ? noise error ?frame error ? parity error 5 interrupt sources with flags: ? transmit data register empty ? transmission complete ? receive data register full ? idle line received ? overrun error detected parity control: ? transmits parity bit ? checks parity of received data byte reduced power consumption mode 11.5.3 general description the interface is externally connected to another device by three pins (see figure 63 ). any sci bidirectional communication requires a minimum of two pins: receive data in (rdi) and transmit data out (tdo): sclk: transmitter clock output. this pin outputs the transmitter data clock for synchronous transmission (no clock pulses on start bit and stop bit, and a software option to send a clock pulse on the last data bit). this can be used to control
on-chip peripherals st72344xx st72345xx 130/247 doc id 12321 rev 5 peripherals that have shift registers (e.g. lcd drivers). the clock phase and polarity are software programmable. tdo: transmit data output. when the transmitter is disabled, the output pin returns to its i/o port configuration. when the transmitter is enabled and nothing is to be transmitted, the tdo pin is at high level. rdi: receive data input is the serial data input. oversampling techniques are used for data recovery by discriminating between valid incoming data and noise. through these pins, serial data is transmitted and received as frames comprising: an idle line prior to transmission or reception a start bit a data word (8 or 9 bits) least significant bit first a stop bit indicating that the frame is complete. this interface uses two types of baud rate generator: a conventional type for commonly-used baud rates, an extended type with a prescaler offering a very wide range of baud rates even with non-standard oscilla tor frequencies.
st72344xx st72345xx on-chip peripherals doc id 12321 rev 5 131/247 figure 63. sci block diagram wake up unit receiver control scisr transmit control tdre tc rdrf idle or nf fe sci control interrupt scicr1 r8 t8 m wake receive data register (rdr) receive shift register read transmit data register (tdr) transmit shift register write rdi tdo (data register) scidr transmitter clock receiver clock receiver rate transmitter rate scibrr scp1 f cpu control control scp0 sct2 sct1 sct0 scr2 scr1scr0 /pr /16 conventional baud rate generator sbk rwu re te ilie rie tcie tie scicr2 scid pce ps pie pe
on-chip peripherals st72344xx st72345xx 132/247 doc id 12321 rev 5 11.5.4 functional description the block diagram of the serial control interface, is shown in figure 63 . it contains six dedicated registers: 2 control registers (scicr1 and scicr2) a status register (scisr) a baud rate register (scibrr) an extended prescaler receiver register (scierpr) an extended prescaler transmitter register (scietpr) refer to the register descriptions in section 11.5.7 for the definitions of each bit. serial data format word length may be selected as being either 8 or 9 bits by programming the m bit in the scicr1 register (see figure 64 ). the tdo pin is in low state during the start bit. the tdo pin is in high state during the stop bit. an idle character is interpreted as an entire frame of ?1?s followed by the start bit of the next frame which contains data. a break character is interpreted on receiving ?0?s for some multiple of the frame period. at the end of the last break frame the transmitter inserts an extra ?1? bit to acknowledge the start bit. transmission and reception are driven by their own baud rate generator.
st72344xx st72345xx on-chip peripherals doc id 12321 rev 5 133/247 figure 64. word length programming 1. lbcl bit controls last data clock pulse. transmitter the transmitter can send data words of either 8 or 9 bits depending on the m bit status. when the m bit is set, word length is 9 bits and the 9th bit (the msb) has to be stored in the t8 bit in the scicr1 register. when the transmit enable bit (te) is set, the data in the transmit shift register is output on the tdo pin. bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 bit8 start bit stop bit next start bit idle frame bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 start bit stop bit next start bit idle frame start bit 9-bit (m bit is set) 8-bit (m bit is reset) possible parity bit possible parity bit break frame start bit extra ?1? data frame break frame start bit extra ?1? data frame next data frame next data frame start bit **** clock clock (1) (1)
on-chip peripherals st72344xx st72345xx 134/247 doc id 12321 rev 5 character transmission during an sci transmission, data shifts out least significant bit first on the tdo pin. in this mode, the scidr register consists of a buffer (tdr) between the internal bus and the transmit shift register (see figure 64 ). procedure: ? select the m bit to define the word length. ? select the desired baud rate using the scibrr and the scietpr registers. ? set the te bit to send an idle frame as first transmission. ? access the scisr register and write the data to send in the scidr register (this sequence clears the tdre bit). repeat this sequence for each data to be transmitted. clearing the tdre bit is always performed by the following software sequence: a) an access to the scisr register b) a write to the scidr register the tdre bit is set by hardware and it indicates: ? the tdr register is empty. ? the data transfer is beginning. ? the next data can be written in the scidr register without overwriting the previous data. this flag generates an interrupt if the tie bit is set and the i bit is cleared in the ccr register. when a transmission is taking place, a write instruction to the scidr register stores the data in the tdr register and which is copied in the shift register at the end of the current transmission. when no transmission is taking place, a writ e instruction to the scidr register places the data directly in the shift register, the data transmission starts, and the tdre bit is immediately set. when a frame transmission is complete (after the stop bit or after the break frame) the tc bit is set and an interrupt is generated if the tcie is set and the i bit is cleared in the ccr register. clearing the tc bit is performed by the following software sequence: a) an access to the scisr register b) a write to the scidr register note: the tdre and tc bits are cleared by the same software sequence. break characters setting the sbk bit loads the sh ift register with a break character. the break frame length depends on the m bit (see figure 64 ). as long as the sbk bit is set, the sci send break frames to the tdo pin. after clearing this bit by software the sci insert a logic 1 bit at the end of the last break frame to guarantee the recognition of the start bit of the next frame. idle characters setting the te bit drives the sci to send an idle frame before the first data frame. clearing and then setting the te bit during a transmission sends an idle frame after the current word.
st72344xx st72345xx on-chip peripherals doc id 12321 rev 5 135/247 note: resetting and setting the te bit causes the data in the tdr register to be lost. therefore the best time to toggle the te bit is when the tdre bit is set, that is, before writing the next byte in the scidr. receiver the sci can receive data words of either 8 or 9 bits. when the m bit is set, word length is 9 bits and the msb is stored in the r8 bit in the scicr1 register. character reception during a sci reception, data shifts in least significant bit first through the rdi pin. in this mode, the scidr register consists or a buffer (rdr) between the internal bus and the received shift register (see figure 63 ). procedure: ? select the m bit to define the word length. ? select the desired baud rate using the scibrr and the scierpr registers. ? set the re bit, this enables the receiver which begins searching for a start bit. when a character is received: ? the rdrf bit is set. it indicates that the content of the shift register is transferred to the rdr. ? an interrupt is generated if the rie bit is set and the i bit is cleared in the ccr register. ? the error flags can be set if a frame error, noise or an overrun error has been detected during reception. clearing the rdrf bit is performed by the following software sequence done by: a) an access to the scisr register b) a read to the scidr register. the rdrf bit must be cleared before the end of the reception of the next character to avoid an overrun error. break character when a break character is received, the sci handles it as a framing error. idle character when an idle frame is detected, there is the same procedure as a data received character plus an interrupt if the ilie bit is set and the i bit is cleared in the ccr register.
on-chip peripherals st72344xx st72345xx 136/247 doc id 12321 rev 5 overrun error an overrun error occurs when a character is received when rdrf has not been reset. data cannot be transferred from the shift register to the rdr register until the rdrf bit is cleared. when a overrun error occurs: ? the or bit is set. ? the rdr content is not lost. ? the shift register is overwritten. ? an interrupt is generated if the rie bit is set and the i bit is cleared in the ccr register. the or bit is reset by an access to the scisr register followed by a scidr register read operation. noise error oversampling techniques are used for data recovery by discriminating between valid incoming data and noise. normal data bits are considered valid if three consecutive samples (8th, 9th, 10th) have the same bit value, otherwise the nf flag is set. in the case of start bit detection, the nf flag is set on the basis of an algorithm combining both valid edge detection and three samples (8th, 9th, 10th). therefore, to prevent the nf flag getting set during start bit reception, there should be a valid edge detection as well as three valid samples. when noise is detected in a frame: ? the nf flag is set at the rising edge of the rdrf bit. ? data is transferred from the shift register to the scidr register. ? no interrupt is generated. however this bit rises at the same time as the rdrf bit which itself generates an interrupt. the nf flag is reset by a scisr register read operation followed by a scidr register read operation. during reception, if a false start bit is detected (e.g. 8th, 9th, 10th samples are 011,101,110), the frame is discarded and the receiving sequence is not started for this frame. there is no rdrf bit set for this frame and the nf flag is set internally (not accessible to the user). this nf flag is accessible along with the rdrf bit when a next valid frame is received. note: if the application start bit is not long enough to match the above requirements, then the nf flag may get set due to the short start bit. in this case, the nf flag may be ignored by the application software when the first valid byte is received. see also noise error causes .
st72344xx st72345xx on-chip peripherals doc id 12321 rev 5 137/247 framing error a framing error is detected when: ? the stop bit is not recognized on reception at the expected time, following either a de-synchronization or excessive noise. ? a break is received. when the framing error is detected: ? the fe bit is set by hardware ? data is transferred from the shift register to the scidr register. ? no interrupt is generated. however this bit rises at the same time as the rdrf bit which itself generates an interrupt. the fe bit is reset by a scisr register read operation followed by a scidr register read operation. figure 65. sci baud rate and extended prescaler block diagram transmitter receiver scietpr scierpr extended prescaler receiver rate control extended prescaler transmitter rate control extended prescaler clock clock receiver rate transmitter rate scibrr scp1 f cpu control control scp0 sct2 sct1 sct0 scr2 scr1scr0 /pr /16 conventional baud rate generator extended receiver prescaler register extended transmitter prescaler register
on-chip peripherals st72344xx st72345xx 138/247 doc id 12321 rev 5 conventional baud rate generation the baud rates for the receiver and transmitter (rx and tx) are set independently and calculated as follows: : with: pr = 1, 3, 4 or 13 (see scp[1:0] bits) tr = 1, 2, 4, 8, 16, 32, 64,128 (see sct[2:0] bits) rr = 1, 2, 4, 8, 16, 32, 64,128 (see scr[2:0] bits) all these bits are in the scibrr register. example: if f cpu is 8 mhz (normal mode) and if pr = 13 and tr = rr = 1, the transmit and receive baud rates are 38400 baud. note: the baud rate registers must not be changed while the transmitter or the receiver is enabled. extended baud rate generation the extended prescaler option gives a very fine tuning on the baud rate, using a 255 value prescaler, whereas the conventional baud rate generator retains industry standard software compatibility. the extended baud rate generator block diagram is shown in figure 65 . the output clock rate sent to the transmitter or to the receiver is the output from the 16 divider divided by a factor ranging from 1 to 255 set in the scierpr or the scietpr register. note: the extended prescaler is activated by setting the scietpr or scierpr register to a value other than zero. the baud rates are calculated as follows: with: etpr = 1, ..., 255 (see scietpr register) erpr = 1, ..., 255 (see scierpr register) receiver muting and wakeup feature in multiprocessor configurations it is often desirable that only the intended message recipient should actively receive the full message contents, thus reducing redundant sci service overhead for all non addressed receivers. the non-addressed devices may be placed in sleep mode by means of the muting function. tx = (16 * pr) * tr f cpu rx = (16 * pr) * rr f cpu tx = 16 * etpr*(pr*tr) f cpu rx = 16 * erpr*(pr*rr) f cpu
st72344xx st72345xx on-chip peripherals doc id 12321 rev 5 139/247 setting the rwu bit by software puts the sci in sleep mode: none of the reception status bits can be set. all the receive interrupts are inhibited. a muted receiver can be woken up in one of the following two ways: by idle line detection if the wake bit is reset, by address mark detection if the wake bit is set. a receiver wakes-up by idle line detection when the receive line has recognized an idle frame. then the rwu bit is reset by hardware but the idle bit is not set. a receiver wakes-up by address mark detection when it received a ?1? as the most significant bit of a word, thus indicating that the message is an address. the reception of this particular word wakes up the receiver, resets the rwu bit and sets the rdrf bit, which allows the receiver to receive this word normally and to use it as an address word. parity control parity control (generation of parity bit in transmission and parity checking in reception) can be enabled by setting the pce bit in the scicr1 register. depending on the frame length defined by the m bit, the possible sci frame formats are as listed in ta bl e 5 6 . note: in case of wakeup by an address mark, the msb bit of the data is taken into account and not the parity bit even parity : the parity bit is calculated to obtain an even number of ?1s? inside the frame made of the 7 or 8 lsb bits (depending on whether m is equal to 0 or 1) and the parity bit. example: data = 00110101; 4 bits set => parity bit is 0 if even parity is selected (ps bit = 0). odd parity : the parity bit is calculated to obtain an odd number of ?1s? inside the frame made of the 7 or 8 lsb bits (depending on whether m is equal to 0 or 1) and the parity bit. example: data = 00110101; 4 bits set => parity bit is 1 if odd parity is selected (ps bit = 1). transmission mode : if the pce bit is set then the msb bit of the data written in the data register is not transmitted but is changed by the parity bit. reception mode : if the pce bit is set then the interface checks if the received data byte has an even number of ?1s? if even parity is selected (ps = 0) or an odd number of ?1s? if odd parity is selected (ps = 1). if the parity check fails, the pe flag is set in the scisr register and an interrupt is generated if pie is set in the scicr1 register. table 56. frame formats m bit pce bit sci frame (1) 1. sb: start bit, stb: stop bit, pb: parity bit. 0 0 | sb | 8 bit data | stb | 1 | sb | 7-bit data | pb | stb | 1 0 | sb | 9-bit data | stb | 1 | sb | 8-bit data pb | stb |
on-chip peripherals st72344xx st72345xx 140/247 doc id 12321 rev 5 sci clock tolerance during reception, each bit is sampled 16 times. the majority of the 8th, 9th and 10th samples is considered as the bit value. for a valid bit detection, all the three samples should have the same value otherwise the noise flag (nf) is set. for example: if the 8th, 9th and 10th samples are 0, 1 and 1 respectively, then the bit value is ?1?, but the noise flag bit is set because the three samples values are not the same. consequently, the bit length must be long enough so that the 8th, 9th and 10th samples have the desired bit value. this means the clock frequency should not vary more than 6/16 (37.5%) within one bit. the sampling clock is resynchronized at each start bit, so that when receiving 10 bits (one start bit, 1 data byte, 1 stop bit), the clock deviation must not exceed 3.75%. note: the internal samp ling clock of the microcontroller sa mples the pin value on every falling edge. therefore, the internal sampling clock and the time the application expects the sampling to take place may be out of sync. for example: if the baud rate is 15.625 kbaud (bit length is 64 s), then the 8th, 9th and 10th samples w ill be at 28 s, 32 s and 36 s respectively (the first sample starting ideally at 0 s). but if the falling edge of the internal clock occurs just before the pin value change s, the samples would then be out of sync by ~4 s. this means the entire bit length must be at least 40 s (36 s for the 10th sample + 4 s for synchronization with the internal sampling clock). clock deviation causes the causes which contribute to the total deviation are: d tra : deviation due to transmitte r error (local oscillator erro r of the transmitter or the transmitter is transmitting at a different baud rate). d quant : error due to the baud rate quantization of the receiver. d rec : deviation of the local oscillator of the receiver: this deviat ion can occur during the reception of one complete sci message assuming that the deviation has been compensated at the beginning of the message. d tcl : deviation due to the transmission line (generally due to the transceivers) all the deviations of the system should be added and compared to the sci clock tolerance: d tra + d quant + d rec + d tcl < 3.75% noise error causes see also description of noise error in receiver . start bit: the noise flag (nf) is set during start bit reception if one of the following conditions occurs: ? a valid falling edge is not detected. a falling edge is c onsidered to be valid if the three consecutive samples before the fallin g edge occurs are dete cted as '1' and,
st72344xx st72345xx on-chip peripherals doc id 12321 rev 5 141/247 after the falling edge occurs, during the sampling of the 16 samples, if one of the samples numbered 3, 5 or 7 is detected as a ?1?. ? during sampling of the 16 samples, if one of the samples numbered 8, 9 or 10 is detected as a ?1?. therefore, a valid start bit must satisfy both the above conditions to prevent the noise flag getting set. data bits: the noise flag (nf) is set during normal data bit reception if the following condition occurs: ? during the sampling of 16 samples, if all three samples numbered 8, 9 and 10 are not the same. the majority of the 8th, 9th and 10th samples is considered as the bit value. therefore, a valid data bit must have samples 8, 9 and 10 at the same value to prevent the noise flag getting set. figure 66. bit sampling in reception mode 11.5.5 low-power modes rdi line sample clock 1234567891011 12 13 14 15 16 sampled values one bit time 6/16 7/16 7/16 table 57. mode description mode description wait no effect on sci. sci interrupts cause the device to exit from wait mode. halt sci registers are frozen. in halt mode, the sci stops transmitting /receiving until halt mode is exited.
on-chip peripherals st72344xx st72345xx 142/247 doc id 12321 rev 5 11.5.6 interrupts the sci interrupt events are connected to the same interrupt vector. these events generate an interrupt if the corresponding enable control bit is set and the interrupt mask in the cc register is reset (rim instruction). 11.5.7 register description status register (scisr) reset value: 1100 0000 (c0h) bit 7 = tdre transmit data register empty. this bit is set by hardware when the content of the tdr register has been transferred into the shift register. an interrupt is generated if the tie bit = 1 in the scicr2 register. it is cleared by a software sequence (an access to the scisr register followed by a write to the scidr register). 0: data is not transferred to the shift register 1: data is transferred to the shift register note: data is not transferred to the shift register until the tdre bit is cleared. bit 6 = tc transmission complete. this bit is set by hardware when transmission of a frame containing data is complete. an interrupt is generated if tcie = 1 in the scicr2 register. it is cleared by a software sequence (an access to the scisr register followed by a write to the scidr register). 0: transmission is not complete 1: transmission is complete note: tc is not set after the transmission of a preamble or a break. bit 5 = rdrf received data ready flag. this bit is set by hardware when the conten t of the rdr register has been transferred to the scidr register. an interrupt is generated if rie = 1 in the scicr2 register. it is table 58. interrupt events interrupt event event flag enable control bit exit from wait exit from halt transmit data register empty tdre tie ye s n o transmission complete tc tcie received data ready to be read rdrf rie overrun error detected or idle line detected idle ilie parity error pe pie 7 0 tdre tc rdrf idle or nf fe pe read-only
st72344xx st72345xx on-chip peripherals doc id 12321 rev 5 143/247 cleared by a software sequence (an access to the scisr register followed by a read to the scidr register). 0: data is not received 1: received data is ready to be read bit 4 = idle idle line detect. this bit is set by hardware when an idle line is detected. an interrupt is generated if the ilie = 1 in the scicr2 register. it is cleared by a software sequence (an access to the scisr register followed by a read to the scidr register). 0: no idle line is detected 1: idle line is detected note: the idle bit is not set again until the rdrf bit has been set itself (that is, a new idle line occurs). bit 3 = or overrun error. this bit is set by hardware when the word currently being received in the shift register is ready to be transferred into the rdr register while rdrf = 1. an interrupt is generated if rie = 1 in the scicr2 register. it is cleared by a software sequence (an access to the scisr register followed by a read to the scidr register). 0: no overrun error 1: overrun error is detected note: when this bit is set, the rdr register content is not lost but the shift register is overwritten. bit 2 = nf noise flag. this bit is set by hardware when noise is detected on a received frame. it is cleared by a software sequence (an access to the scisr register followed by a read to the scidr register). 0: no noise is detected 1: noise is detected note: this bit does not generate interrupt as it ap pears at the same time as the rdrf bit which itself generates an interrupt. bit 1 = fe framing error. this bit is set by hardware when a desynchronization, excessive noise or a break character is detected. it is cleared by a software sequence (an access to the scisr register followed by a read to the scidr register). 0: no framing error is detected 1: framing error or break character is detected note: this bit does not generate an in terrupt as it appears at the sa me time as the rdrf bit which itself generates an interrupt. if the word currently being transferred causes both frame error and overrun error, it is transferred and only the or bit is set. bit 0 = pe parity error. this bit is set by hardware when a parity error occurs in receiver mode. it is cleared by a software sequence (a read to the status register followed by an access to the scidr data register). an interrupt is generated if pie = 1 in the scicr1 register. 0: no parity error 1: parity error
on-chip peripherals st72344xx st72345xx 144/247 doc id 12321 rev 5 control register 1 (scicr1) reset value: x000 0000 (x0h) bit 7 = r8 receive data bit 8. this bit is used to store the 9th bit of the received word when m = 1. bit 6 = t8 transmit data bit 8. this bit is used to store the 9th bit of the transmitted word when m = 1. bit 5 = scid disabled for low power consumption when this bit is set the sci prescalers and outputs are stopped and the end of the current byte transfer in order to reduce power consumption.this bit is set and cleared by software. 0: sci enabled 1: sci prescaler and outputs disabled bit 4 = m word length. this bit determines the word length. it is set or cleared by software. 0: 1 start bit, 8 data bits, 1 stop bit 1: 1 start bit, 9 data bits, 1 stop bit note: the m bit must not be modified during a data transfer (both transmission and reception). bit 3 = wake wakeup method. this bit determines the sci wake-up method, it is set or cleared by software. 0: idle line 1: address mark bit 2 = pce parity control enable. this bit selects the hardware parity control (generation and detection). when the parity control is enabled, the computed parity is inserted at the msb position (9th bit if m = 1; 8th bit if m = 0) and parity is checked on the received data. this bit is set and cleared by software. once it is set, pce is active after the current byte (in reception and in transmission). 0: parity control disabled 1: parity control enabled bit 1 = ps parity selection. this bit selects the odd or even parity when the parity generation/detection is enabled (pce bit set). it is set and cleared by software. the parity is selected after the current byte. 0: even parity 1: odd parity 7 0 r8 t8 scid m wake pce ps pie read/write
st72344xx st72345xx on-chip peripherals doc id 12321 rev 5 145/247 bit 0 = pie parity interrupt enable. this bit enables the interrupt capability of the hardware parity control when a parity error is detected (pe bit set). it is set and cleared by software. 0: parity error interrupt disabled 1: parity error interrupt enabled control register 2 (scicr2) reset value: 0000 0000 (00h) bit 7 = tie transmitter interrupt enable . this bit is set and cleared by software. 0: interrupt is inhibited 1: an sci interrupt is generated whenever tdre = 1 in the scisr register bit 6 = tcie transmission complete interrupt enable this bit is set and cleared by software. 0: interrupt is inhibited 1: an sci interrupt is generated whenever tc = 1 in the scisr register bit 5 = rie receiver interrupt enable . this bit is set and cleared by software. 0: interrupt is inhibited 1: an sci interrupt is generated whenever or = 1 or rdrf = 1 in the scisr register bit 4 = ilie idle line interrupt enable. this bit is set and cleared by software. 0: interrupt is inhibited 1: an sci interrupt is generated whenever idle = 1 in the scisr register. bit 3 = te transmitter enable. this bit enables the transmitter. it is set and cleared by software. 0: transmitter is disabled 1: transmitter is enabled note: during transmission, a ?0? pulse on the te bit (?0? followed by ?1?) sends a preamble (idle line) after the current word. when te is set there is a 1 bit-time delay before the transmission starts. bit 2 = re receiver enable. this bit enables the receiver. it is set and cleared by software. 0: receiver is disabled 1: receiver is enabled and begins searching for a start bit 7 0 tie tcie rie ilie te re rwu sbk read/write
on-chip peripherals st72344xx st72345xx 146/247 doc id 12321 rev 5 bit 1 = rwu receiver wake-up. this bit determines if the sci is in mute mode or not. it is set and cleared by software and can be cleared by hardware when a wake-up sequence is recognized. 0: receiver in active mode 1: receiver in mute mode note: before selecting mute mode (by setting the rwu bit) the sci must first receive a data byte, otherwise it cannot function in mute mode with wake-up by idle line detection. in address mark detection wake-up configuration (wake bit = 1) the rwu bit cannot be modified by software while the rdrf bit is set. bit 0 = sbk send break. this bit set is used to send break characters. it is set and cleared by software. 0: no break character is transmitted 1: break characters are transmitted note: if the sbk bit is set to ?1? and then to ?0?, the transmitter sends a break word at the end of the current word. data register (scidr) reset value: undefined contains the received or transmitted data character, depending on whether it is read from or written to. the data register performs a double function (r ead and write) since it is composed of two registers, one for transmission (t dr) and one for reception (rdr). the tdr register provides the parallel interface between the internal bus and the output shift register (see figure 63 ). the rdr register provides the parallel interface between the input shift register and the internal bus (see figure 63 ). baud rate register (scibrr) reset value: 0000 0000 (00h) bits 7:6 = scp[1:0] first sci prescaler these 2 prescaling bits allow several standard clock division ranges as shown in figure 59 . 7 0 dr7 dr6 dr5 dr4 dr3 dr2 dr1 dr0 read/write 7 0 scp1 scp0 sct2 sct1 sct0 scr2 scr1 scr0 read/write
st72344xx st72345xx on-chip peripherals doc id 12321 rev 5 147/247 bits 5:3 = sct[2:0] sci transmitter rate divisor these 3 bits, in conjunction with the scp1 and scp0 bits define the total division applied to the bus clock to yield the transmit rate clock in conventional baud rate generator mode. note: this tr factor is used only when the etpr fine tuning factor is equal to 00h; otherwise, tr is replaced by the (tr*etpr) dividing factor. bits 2:0 = scr[2:0] sci receiver rate divisor. these 3 bits, in conjunction with the scp1 and scp0 bits define the total division applied to the bus clock to yield the rece ive rate clock in conventional baud rate generator mode. table 59. scp[1:0] configuration pr prescaling factor scp1 scp0 1 0 0 31 4 1 0 13 1 table 60. sct[2:0] configuration tr dividing factor sct2 sct1 sct0 1 0 0 0 21 4 1 0 81 16 1 0 0 32 1 64 1 0 128 1 table 61. scr[2:0] configuration rr dividing factor scr2 scr1 scr0 1 0 0 0 21 4 1 0 81 16 1 0 0 32 1 64 1 0 128 1
on-chip peripherals st72344xx st72345xx 148/247 doc id 12321 rev 5 note: this rr factor is used only when the erpr fine tuning factor is equal to 00h; otherwise, rr is replaced by the (rr*erpr) dividing factor. extended receive prescaler division register (scierpr) reset value: 0000 0000 (00h) bits 7:0 = erpr[7:0] 8-bit extended receive prescaler register. the extended baud rate generator is activated when a value other than 00h is stored in this register. the clock frequency from the 16 divider (see figure 65 ) is divided by the binary factor set in the scierpr register (in the range 1 to 255). the extended baud rate generator is not active after a reset. extended transmit prescaler division register (scietpr) reset value:0000 0000 (00h) bits 7:0 = etpr[7:0] 8-bit extended transmit prescaler register. the extended baud rate generator is activated when a value other than 00h is stored in this register. the clock frequency from the 16 divider (see figure 65 ) is divided by the binary factor set in the scietpr register (in the range 1 to 255). the extended baud rate generator is not active after a reset. 7 0 erpr7 erpr6 erpr5 erpr4 erpr3 erpr2 erpr1 erpr0 read/write 7 0 etpr7 etpr6 etpr5 etpr4 etpr3 etpr2 etpr1 etpr0 read/write table 62. baud rate selection symbol parameter conditions standard baud rate unit f cpu accuracy vs. standard prescaler f tx f rx communication frequency 8mhz ~0.16% conventional mode tr (or rr) = 128, pr = 13 tr (or rr) = 32, pr = 13 tr (or rr) = 16, pr =13 tr (or rr) = 8, pr = 13 tr (or rr) = 4, pr = 13 tr (or rr) = 16, pr = 3 tr (or rr) = 2, pr = 13 tr (or rr) = 1, pr = 13 300 1200 2400 4800 9600 10400 19200 38400 ~300.48 ~1201.92 ~2403.84 ~4807.69 ~9615.38 ~10416.67 ~19230.77 ~38461.54 hz ~0.79% extended mode etpr (or erpr) = 35, tr (or rr) = 1, pr = 1 14400 ~14285.71
st72344xx st72345xx on-chip peripherals doc id 12321 rev 5 149/247 table 63. sci register map and reset values address (hex.) register label 76543210 0050h scisr reset value tdre 1 tc 1 rdrf 0 idle 0 or 0 nf 0 fe 0 pe 0 0051h scidr reset value msb xxxxxxx lsb x 0052h scibrr reset value scp1 0 scp0 0 sct2 0 sct1 0 sct0 0 scr2 0 scr1 0 scr0 0 0053h scicr1 reset value r8 x t8 0 scid 0 m 0 wake 0 pce 0 ps 0 pie 0 0054h scicr2 reset value tie 0 tcie 0 rie 0 ilie 0 te 0 re 0 rwu 0 sbk 0 0056h scierpr reset value msb 0000000 lsb 0 0057h scipetpr reset value msb 0000000 lsb 0
on-chip peripherals st72344xx st72345xx 150/247 doc id 12321 rev 5 11.6 i 2 c bus interface (i2c) 11.6.1 introduction the i 2 c bus interface serves as an interface between the microcontroller and the serial i 2 c bus. it provides both multimaster and slave functions, and controls all i 2 c bus-specific sequencing, protocol, arbitration and timing. it supports fast i 2 c mode (400 khz). 11.6.2 main features parallel-bus/i 2 c protocol converter multi-master capability 7-bit/10-bit addressing transmitter/receiver flag end-of-byte transmission flag transfer problem detection i 2 c master features clock generation i 2 c bus busy flag arbitration lost flag end of byte transmission flag transmitter/receiver flag start bit detection flag start and stop generation i 2 c slave features stop bit detection i 2 c bus busy flag detection of misplaced start or stop condition programmable i 2 c address detection transfer problem detection end-of-byte transmission flag transmitter/receiver flag 11.6.3 general description in addition to receiving and transmitting data, this interface converts it from serial to parallel format and vice versa, using either an interrupt or polled handshake. the interrupts are enabled or disabled by software. the interface is connected to the i 2 c bus by a data pin (sdai) and by a clock pin (scli). it can be connected both with a standard i 2 c bus and a fast i 2 c bus. this selection is made by software.
st72344xx st72345xx on-chip peripherals doc id 12321 rev 5 151/247 mode selection the interface can operate in the four following modes: slave transmitter/receiver master transmitter/receiver by default, it operates in slave mode. the interface automatically switches from slave to master after it generates a start condition and from master to slave in case of arbitration loss or a stop generation, allowing then multi-master capability. communication flow in master mode, it initiates a data transfer and generates the clock signal. a serial data transfer always begins with a start condition and ends with a stop condition. both start and stop conditions are generated in master mode by software. in slave mode, the interface is capable of recognizing its own address (7 or 10-bit), and the general call address. the general call address detection may be enabled or disabled by software. data and addresses are transferred as 8-bit bytes, msb first. the first byte(s) following the start condition contain the address (one in 7-bit mode, two in 10-bit mode). the address is always transmitted in master mode. a 9th clock pulse follows the 8 clock cycles of a byte transfer, during which the receiver must send an acknowledge bit to the transmitter. refer to figure 67 . figure 67. i 2 c bus protocol acknowledge may be enabled and disabled by software. the i 2 c interface address and/or general call address can be selected by software. the speed of the i 2 c interface may be selected between standard (up to 100 khz) and fast i 2 c (up to 400 khz). sda/scl line control transmitter mode: the interface holds the clock line low before transmission to wait for the microcontroller to write the byte in the data register. receiver mode: the interface holds the clock line low after reception to wait for the microcontroller to read the byte in the data register. the scl frequency (f scl ) is controlled by a programmable clock divider which depends on the i 2 c bus mode. scl sda 12 8 9 msb ack stop start condition condition
on-chip peripherals st72344xx st72345xx 152/247 doc id 12321 rev 5 when the i 2 c cell is enabled, the sda and scl ports must be configured as floating inputs. in this case, the value of the external pull-up resistor used depends on the application. when the i 2 c cell is disabled, the sda and scl ports revert to being standard i/o port pins. figure 68. i 2 c interface block diagram 11.6.4 functional description refer to the cr, sr1 and sr2 registers in section 11.6.7 . for the bit definitions. by default the i 2 c interface operates in slave mode (m/sl bit is cleared) except when it initiates a transmit or receive sequence. first the interface frequency must be configured using the fri bits in the oar2 register. slave mode as soon as a start condition is detected, the address is received from the sda line and sent to the shift register; then it is compared with the address of the interface or the general call address (if selected by software). note: in 10-bit addressing mode, the comparison includes the header sequence (11110xx0) and the two most significant bits of the address. header matched (10-bit mode only): the interface generates an acknowledge pulse if the ack bit is set. data register (dr) data shift register comparator own address register 1 (oar1) clock control register (ccr) status register 1 (sr1) control register (cr) control logic status register 2 (sr2) interrupt clock control data control scl or scli sda or sdai own address register 2 (oar2)
st72344xx st72345xx on-chip peripherals doc id 12321 rev 5 153/247 address not matched : the interface ignores it and waits for another start condition. address matched : the interface generates in sequence: acknowledge pulse if the ack bit is set. evf and adsl bits are set with an interrupt if the ite bit is set. then the interface waits for a read of the sr1 register, holding the scl line low (see figure 69 transfer sequencing ev1). next, in 7-bit mode read the dr register to determine from the least significant bit (data direction bit) if the slave must enter receiver or transmitter mode. in 10-bit mode, after receiving the address sequence the slave is always in receive mode. it will enter transmit mode on rece iving a repeated start condit ion followed by the header sequence with matching address bits and the least significant bit set (11110xx1). slave receiver following the address reception and after sr1 register has been read, the slave receives bytes from the sda line into the dr register via the internal shift register. after each byte the interface generates in sequence: acknowledge pulse if the ack bit is set evf and btf bits are set with an interrupt if the ite bit is set. then the interface waits for a read of the sr1 register followed by a read of the dr register, holding the scl line low (see figure 69 transfer sequencing ev2). slave transmitter following the address reception and after sr1 register has been read, the slave sends bytes from the dr register to the sda line via the internal shift register. the slave waits for a read of the sr1 register followed by a write in the dr register, holding the scl line low (see figure 69 transfer sequencing ev3). when the acknowledge pulse is received: the evf and btf bits are set by hardware with an interrupt if the ite bit is set. closing slave communication after the last data byte is transferred a stop condition is generated by the master. the interface detects this condition and sets: evf and stopf bits with an interrupt if the ite bit is set. then the interface waits for a read of the sr2 register (see figure 69 transfer sequencing ev4). error cases berr : detection of a stop or a start condition during a byte transfer. in this case, the evf and the berr bits are set with an interrupt if the ite bit is set. if it is a stop then the interface discards the data, released the lines and waits for another start condition. if it is a start then the interface discards the data and waits for the next slave address on the bus. af : detection of a non-acknowledge bit. in this case, the evf and af bits are set with an interrupt if the ite bit is set. the af bit is cleared by reading the i2csr2 register. however, if read before the completion of the transmission, the af flag will be set again, thus possibly generating a
on-chip peripherals st72344xx st72345xx 154/247 doc id 12321 rev 5 new interrupt. software must ensure either that the scl line is back at 0 before reading the sr2 register, or be able to correctly handle a second interrupt during the 9th pulse of a transmitted byte. note: in both cases, scl line is not held low; howe ver, the sda line can remain low if the last bits transmitted are all 0. it is then necessary to release both lines by software. the scl line is not held low while af=1 but by other flags (sb or btf) that are set at the same time. how to release the sda / scl lines set and subsequently clear the stop bit while btf is set. the sda/scl lines are released after the transfer of the current byte. smbus compatibility st7 i 2 c is compatible with smbus v1.1 protocol. it supports all smbus addressing modes, smbus bus protocols and crc-8 packet error checking. refer to an1713: smbus slave driver for st7 i 2 c peripheral. master mode to switch from default slave mode to master mode a start condition generation is needed. start condition setting the start bit while the busy bit is cleared causes the interface to switch to master mode (m/sl bit set) and generates a start condition. once the start condition is sent: the evf and sb bits are set by hardware with an interrupt if the ite bit is set. then the master waits for a read of the sr1 register followed by a write in the dr register with the slave address, holding the scl line low (see figure 69 transfer sequencing ev5). slave address transmission then the slave address is sent to the sda line via the internal shift register. in 7-bit addressing mode, one address byte is sent. in 10-bit addressing mode, sending the first byte including the header sequence causes the following event: the evf bit is set by hardware with interrupt generation if the ite bit is set. then the master waits for a read of the sr1 register followed by a write in the dr register, holding the scl line low (see figure 69 transfer sequencing ev9). then the second address byte is sent by the interface. after completion of this transfer (and acknowledge from the slave if the ack bit is set): the evf bit is set by hardware with interrupt generation if the ite bit is set. then the master waits for a read of the sr1 register followed by a write in the cr register (for example set pe bit), holding the scl line low (see figure 69 transfer sequencing ev6). next the master must enter receiver or transmitter mode.
st72344xx st72345xx on-chip peripherals doc id 12321 rev 5 155/247 note: in 10-bit addressing mode, to switch the master to receiver mode, software must generate a repeated start condition and resend the header sequence with the least significant bit set (11110xx1). master receiver following the address transmission and after sr1 and cr registers have been accessed, the master receives bytes from the sda line into the dr register via the internal shift register. after each byte the interface generates in sequence: acknowledge pulse if the ack bit is set evf and btf bits are set by hardware with an interrupt if the ite bit is set. then the interface waits for a read of the sr1 register followed by a read of the dr register, holding the scl line low (see figure 69 transfer sequencing ev7). to close the communication: before reading the last byte from the dr register, set the stop bit to generate the stop condition. the interface goes automatically back to slave mode (m/sl bit cleared). note: in order to generate the non-acknowledge pulse after the last received data byte, the ack bit must be cleared just before reading the second last data byte. master transmitter following the address transmission and after sr1 register has been read, the master sends bytes from the dr register to the sda line via the internal shift register. the master waits for a read of the sr1 register followed by a write in the dr register, holding the scl line low (see figure 69 transfer sequencing ev8). when the acknowledge bit is received, the interface sets: evf and btf bits with an interrupt if the ite bit is set. to close the communication: after writing the last byte to the dr register, set the stop bit to generate the stop condition. the interface goes automatically back to slave mode (m/sl bit cleared). error cases berr : detection of a stop or a start condition during a byte transfer. in this case, the evf and berr bits are set by hardware with an interrup t if ite is set. note that berr will not be set if an error is detected during the first pulse of each 9-bit transaction: single master mode if a start or stop is issued during the firs t pulse of a 9-bit transaction, the berr flag will not be set and transfer will c ontinue however the busy flag will be reset. to work around this, slave devices should issue a nack when they receive a misplaced start or stop. the reception of a nack or busy by the master in the middle of communication gives the possibility to re -initiate transmission. multimaster mode normally the berr bit would be set whenever unauthorized transmission takes place while transfer is already in progress. however, an issue will arise if an external master generates an unauthorized start or stop while the i 2 c master is on the first pulse of a 9-bit transaction. it is possible to work around this by polling the busy bit during i 2 c
on-chip peripherals st72344xx st72345xx 156/247 doc id 12321 rev 5 master mode transmission. the resetting of the busy bit can then be handled in a similar manner as the berr flag being set. af : detection of a non-acknowledge bit. in this case, the evf and af bits are set by hardware with an interrupt if the ite bit is set. to resume, set the start or stop bit. the af bit is cleared by reading the i2csr2 register. however, if read before the completion of the transmission, the af flag will be set again, thus possibly generating a new interrupt. software must ensure either that the scl line is back at 0 before reading the sr2 register, or be able to correctly handle a second interrupt during the 9th pulse of a transmitted byte. arlo: detection of an arbitration lost condition. in this case the arlo bit is set by hardware (with an interrupt if the ite bit is set and the interface goes automatically back to slave mode (the m/sl bit is cleared). note: in all these cases, the scl lin e is not held low; however, the sda line can remain low if the last bits transmitted are all 0. it is then necessary to release both lines by software. the scl line is not held low while af=1 but by other flags (sb or btf) that are set at the same time.
st72344xx st72345xx on-chip peripherals doc id 12321 rev 5 157/247 figure 69. transfer sequencing legend: s = start, s r = repeated start, p = stop, a = acknowledge, na = non- acknowledge, evx = event (with interrupt if ite=1) ev1: evf=1, adsl=1, cleared by reading sr1 register. ev2: evf=1, btf=1, cleared by reading sr1 register followed by reading dr register. ev3: evf=1, btf=1, cleared by reading sr1 register followed by writing dr register. ev3-1: evf=1, af=1, btf=1; af is cleared by reading sr1 register. btf is cleared by releasing the lines (stop=1, stop=0) or by writing dr register (dr=ffh). note: if lines are released by stop=1, stop=0, the subsequent ev4 is not seen. ev4: evf=1, stopf=1, cleared by reading sr2 register. ev5: evf=1, sb=1, cleared by reading sr1 register followed by writing dr register. 7-bit slave receiver: 7-bit slave transmitter: 7-bit master receiver: 7-bit master transmitter: 10-bit slave receiver: 10-bit slave transmitter: 10-bit master transmitter 10-bit master receiver: s address a data1 a data2 a ..... datan a p ev1 ev2 ev2 ev2 ev4 s address a data1 a data2 a ..... datan na p ev1 ev3 ev3 ev3 ev3-1 ev4 s address a data1 a data2 a ..... datan na p ev5 ev6 ev7 ev7 ev7 s address a data1 a data2 a ..... datan a p ev5 ev6 ev8 ev8 ev8 ev8 s header a address a data1 a ..... datan a p ev1 ev2 ev2 ev4 s r header a data1 a ..... datan a p ev1 ev3 ev3 ev3-1 ev4 s header a address a data1 a ..... datan a p ev5 ev9 ev6 ev8 ev8 ev8 s r header a data1 a ..... datan a p ev5 ev6 ev7 ev7
on-chip peripherals st72344xx st72345xx 158/247 doc id 12321 rev 5 ev6: evf=1, cleared by reading sr1 register followed by writing cr register (for example pe=1). ev7: evf=1, btf=1, cleared by reading sr1 register followed by reading dr register. ev8: evf=1, btf=1, cleared by reading sr1 register followed by writing dr register. ev9: evf=1, add10=1, cleared by reading sr1 register followed by writing dr register. 11.6.5 low-power modes 11.6.6 interrupts figure 70. event flags and interrupt generation table 64. mode description mode description wait no effect on i 2 c interface. i 2 c interrupts cause the device to exit from wait mode. halt i 2 c registers are frozen. in halt mode, the i 2 c interface is inactive and does not acknowledge data on the bus. the i 2 c interface resumes operation when the mcu is woken up by an interrupt with ?exit from halt mode? capability. table 65. interrupt events (1) interrupt event event flag enable control bit exit from wait exit from halt 10-bit address sent event (master mode) add10 ite ye s n o end of byte transfer event btf yes no address matched event (slave mode) adsl yes no start bit generation event (master mode) sb yes no acknowledge failure event af yes no stop detection event (slave mode) stopf yes no arbitration lost event (multim aster configuration) arlo yes no bus error event berr yes no btf adsl sb af stopf arlo berr evf interrupt ite * * evf can also be set by ev6 or an error from the sr2 register. add10
st72344xx st72345xx on-chip peripherals doc id 12321 rev 5 159/247 11.6.7 register description i 2 c control register (cr) reset value: 0000 0000 (00h) bits 7:6 = reserved. forced to 0 by hardware. bit 5 = pe peripheral enable. this bit is set and cleared by software. 0: peripheral disabled 1: master/slave capability note: when pe=0, all the bits of the cr register and the sr register except the stop bit are reset. all outputs are released while pe=0 when pe=1, the corresponding i/o pins are selected by hardware as alternate functions. to enable the i 2 c interface, write the cr register twice with pe=1 as the first write only activates the interface (only pe is set). bit 4 = engc enable general call. this bit is set and cleared by software. it is also cleared by hardware when the interface is disabled (pe=0). the 00h general call address is acknowledged (01h ignored). 0: general call disabled 1: general call enabled note: in accordance with the i2c standard, when gcal addressing is enabled, an i2c slave can only receive data. it will not transmit data to the master. bit 3 = start generation of a start condition . this bit is set and cleared by software. it is also cleared by hardware when the interface is disabled (pe=0) or when the start condition is sent (with interrupt generation if ite=1). in master mode: 0: no start generation 1: repeated start generation in slave mode: 0: no start generation 1: start generation when the bus is free 1. the i 2 c interrupt events are connected to the same inte rrupt vector (see interrupts chapter). they generate an interrupt if the corresponding enable control bi t is set and the i-bit in the cc register is reset (rim instruction). 7 0 0 0 pe engc start ack stop ite read / write
on-chip peripherals st72344xx st72345xx 160/247 doc id 12321 rev 5 bit 2 = ack acknowledge enable. this bit is set and cleared by software. it is also cleared by hardware when the interface is disabled (pe=0). 0: no acknowledge returned 1: acknowledge returned after an address byte or a data byte is received bit 1 = stop generation of a stop condition . this bit is set and cleared by software. it is also cleared by hardware in master mode. note: this bit is not cleared when the interface is disabled (pe=0). in master mode: 0: no stop generation 1: stop generation after the current byte transfer or after the current start condition is sent. the stop bit is cleared by hardware when the stop condition is sent. in slave mode: 0: no stop generation 1: release the scl and sda lines after the current byte transfer (btf=1). in this mode the stop bit has to be cleared by software. bit 0 = ite interrupt enable. this bit is set and cleared by software and cleared by hardware when the interface is disabled (pe=0). 0: interrupts disabled 1: interrupts enabled refer to figure 70 for the relationship between the events and the interrupt. scl is held low when the add10, sb, btf or adsl flags or an ev6 event (see figure 69 ) is detected. i 2 c status register 1 (sr1) reset value: 0000 0000 (00h) 7 0 evf add10 tra busy btf adsl m/sl sb read only
st72344xx st72345xx on-chip peripherals doc id 12321 rev 5 161/247 bit 7 = evf event flag. this bit is set by hardware as soon as an event occurs. it is cleared by software reading sr2 register in case of error event or as described in figure 69 . it is also cleared by hardware when the interface is disabled (pe=0). 0: no event 1: one of the following events has occurred: btf=1 (byte received or transmitted) adsl=1 (address matched in slave mode while ack=1) sb=1 (start condition generated in master mode) af=1 (no acknowledge received after byte transmission) stopf=1 (stop condition detected in slave mode) arlo=1 (arbitration lost in master mode) berr=1 (bus error, misplaced start or stop condition detected) add10=1 (master has sent header byte) address byte successfully tr ansmitted in master mode. bit 6 = add10 10-bit addressing in master mode . this bit is set by hardware when the master has sent the first byte in 10-bit address mode. it is cleared by software reading sr2 register followed by a write in the dr register of the second address byte. it is also cleared by hardware when the peripheral is disabled (pe=0). 0: no add10 event occurred. 1: master has sent first address byte (header) bit 5 = tra transmitter/receiver. when btf is set, tra=1 if a data byte has been transmitted. it is cleared automatically when btf is cleared. it is also cleared by hardware after detection of stop condition (stopf=1), loss of bus arbitration (arlo=1) or when the interface is disabled (pe=0). 0: data byte received (if btf=1) 1: data byte transmitted bit 4 = busy bus busy . this bit is set by hardware on detection of a start condition and cleared by hardware on detection of a stop condition. it indicates a communication in progress on the bus. the busy flag of the i2csr1 register is cleared if a bus error occurs. 0: no communication on the bus 1: communication ongoing on the bus bit 3 = btf byte transfer finished. this bit is set by hardware as soon as a byte is correctly received or transmitted with interrupt generation if ite=1. it is cleared by software reading sr1 register followed by a read or write of dr register. it is also cleared by hardware when the interface is disabled (pe=0). following a byte transmission, this bit is set after reception of the acknowledge clock pulse. in case an address byte is sent, this bit is set only after the ev6 event (see
on-chip peripherals st72344xx st72345xx 162/247 doc id 12321 rev 5 figure 69 ). btf is cleared by reading sr1 register followed by writing the next byte in dr register. following a byte reception, this bit is set after transmission of the acknowledge clock pulse if ack=1. btf is cleared by reading sr1 register followed by reading the byte from dr register. the scl line is held low while btf=1. 0: byte transfer not done 1: byte transfer succeeded bit 2 = adsl address matched (slave mode). this bit is set by hardware as soon as the received slave address matched with the oar register content or a general call is recognized. an interrupt is generated if ite=1. it is cleared by software reading sr1 register or by hardware when the interface is disabled (pe=0). the scl line is held low while adsl=1. 0: address mismatched or not received 1: received address matched bit 1 = m/sl master/slave. this bit is set by hardware as soon as the interface is in master mode (writing start=1). it is cleared by hardware after detecting a stop condition on the bus or a loss of arbitration (arlo=1). it is also cleared when the interface is disabled (pe=0). 0: slave mode 1: master mode bit 0 = sb start bit (master mode). this bit is set by hardware as soon as the start condition is generated (following a write start=1). an interrupt is generated if ite=1. it is cleared by software reading sr1 register followed by writing the address byte in dr register. it is also cleared by hardware when the interface is disabled (pe=0). 0: no start condition 1: start condition generated i 2 c status register 2 (sr2) reset value: 0000 0000 (00h) bit 7:5 = reserved. forced to 0 by hardware. 7 0 0 0 0 af stopf arlo berr gcal read only
st72344xx st72345xx on-chip peripherals doc id 12321 rev 5 163/247 bit 4 = af acknowledge failure . this bit is set by hardware when no acknowledge is returned. an interrupt is generated if ite=1. it is cleared by software reading sr2 register or by hardware when the interface is disabled (pe=0). the scl line is not held low wh ile af=1 but by other flags (sb or btf) that are set at the same time. 0: no acknowledge failure 1: acknowledge failure bit 3 = stopf stop detection (slave mode). this bit is set by hardware when a stop condition is detected on the bus after an acknowledge (if ack=1). an interrupt is generated if ite=1. it is cleared by software reading sr2 register or by hardware when the interface is disabled (pe=0). the scl line is not held low while stopf=1. 0: no stop condition detected 1: stop condition detected bit 2 = arlo arbitration lost . this bit is set by hardware when the interface loses the arbitration of the bus to another master. an interrupt is generated if ite=1. it is cleared by software reading sr2 register or by hardware when the interface is disabled (pe=0). after an arlo event the interface switches back automatically to slave mode (m/sl=0). the scl line is not he ld low while arlo=1. 0: no arbitration lost detected 1: arbitration lost detected note: in a multimaster environment, when the interface is configured in master receive mode it does not perform arbitration during the reception of the acknowledge bit. mishandling of the arlo bit from the i2csr2 register may occur when a second master simultaneously requests the same data from the same slave and the i 2 c master does not acknowledge the data. the arlo bit is then left at 0 instead of being set. bit 1 = berr bus error. this bit is set by hardware when the interface detects a misplaced start or stop condition. an interrupt is generated if ite=1. it is cleared by software reading sr2 register or by hardware when the interface is disabled (pe=0). the scl line is not held low while berr=1. 0: no misplaced start or stop condition 1: misplaced start or stop condition note: if a bus error occurs, a stop or a repeated start condition should be generated by the master to re-synchronize communication, get the transmission acknowledged and the bus released for further communication bit 0 = gcal general call (slave mode). this bit is set by hardware when a general call address is detected on the bus while engc=1. it is cleared by hardware detecting a stop condition (stopf=1) or when the interface is disabled (pe=0). 0: no general call address detected on bus 1: general call address detected on bus
on-chip peripherals st72344xx st72345xx 164/247 doc id 12321 rev 5 i 2 c clock control register (ccr) reset value: 0000 0000 (00h) bit 7 = fm/sm fast/standard i 2 c mode. this bit is set and cleared by software. it is not cleared when the interface is disabled (pe=0). 0: standard i 2 c mode 1: fast i 2 c mode bit 6:0 = cc[6:0] 7-bit clock divider. these bits select the speed of the bus (f scl ) depending on the i 2 c mode. they are not cleared when the interface is disabled (pe=0). refer to the electrical characteristics section for the table of values. note: the programmed f scl assumes no load on scl and sda lines. 7 0 fm/sm cc6 cc5 cc4 cc3 cc2 cc1 cc0 read / write
st72344xx st72345xx on-chip peripherals doc id 12321 rev 5 165/247 i 2 c data register (dr) reset value: 0000 0000 (00h) bits 7:0 = d[7:0] 8-bit data register. these bits contain the byte to be received or transmitted on the bus. transmitter mode: byte transmission start automatically when the software writes in the dr register. receiver mode: the first data byte is received automatically in the dr register using the least significant bit of the address. then, the following data bytes are received one by one after reading the dr register. i 2 c own address register (oar1) reset value: 0000 0000 (00h) 7-bit addressing mode bits 7:1 = add[7:1] interface address . these bits define the i 2 c bus address of the interface. they are not cleared when the interface is disabled (pe=0). bit 0 = add0 address direction bit. this bit is don?t care, the interface acknowledges either 0 or 1. it is not cleared when the interface is disabled (pe=0). note: address 01h is always ignored. 10-bit addressing mode bit 7:0 = add[7:0] interface address . these are the least significant bits of the i 2 c bus address of the interface. they are not cleared when the interface is disabled (pe=0). 7 0 d7 d6 d5 d4 d3 d2 d1 d0 read / write 7 0 add7 add6 add5 add4 add3 add2 add1 add0 read / write
on-chip peripherals st72344xx st72345xx 166/247 doc id 12321 rev 5 i 2 c own address register (oar2) reset value: 0100 0000 (40h) bit 7:6 = fr[1:0] frequency bits. these bits are set by software only when the interface is disabled (pe=0). to configure the interface to i 2 c specified delays select the value corresponding to the microcontroller frequency f cpu . bits 5:3 = reserved bits 2:1 = add[9:8] interface address . these are the most significant bits of the i 2 c bus address of the interface (10-bit mode only). they are not cleared when the interface is disabled (pe=0). bit 0 = reserved. 7 0 fr1 fr0 0 0 0 add9 add8 0 read / write table 66. fr[1:0] configuration f cpu fr1 fr0 < 6 mhz 0 0 6 to 8 mhz 0 1 table 67. i 2 c register map and reset values address (hex.) register label 765 4 3210 0058h i2ccr reset value 0 0 pe 0 engc 0 start 0 ack 0 stop 0 ite 0 0059h i2csr1 reset value evf 0 add10 0 tra 0 busy 0 btf 0 adsl 0 m/sl 0 sb 0 005ah i2csr2 reset value 0 0 0 af 0 stopf 0 arlo 0 berr 0 gcal 0 005bh i2cccr reset value fm/sm 0 cc6 0 cc5 0 cc4 0 cc3 0 cc2 0 cc1 0 cc0 0 005ch i2coar1 reset value add7 0 add6 0 add5 0 add4 0 add3 0 add2 0 add1 0 add0 0 005dh i2coar2 reset value fr1 0 fr0 10 0 0 add9 0 add8 00 005eh i2cdr reset value msb 000 0 000 lsb 0
st72344xx st72345xx on-chip peripherals doc id 12321 rev 5 167/247 11.7 i2c triple slave in terface with dma (i2c3s) 11.7.1 introduction the i 2 c3s interface provides three i2c slave fu nctions, supporting both standard (up to 100 khz) and fast i 2 c mode (100 to 400 khz). special features are provided for: full-speed emulation of standard i 2 c e 2 proms receiving commands to perform user-defined operations such as iap 11.7.2 main features three user configurable independent slave addresses can be individually enabled 2x 256 bytes and 1x 128 bytes buffers with fixed addresses in ram 7-bit addressing dma transfer to/from i 2 c bus and ram standard (transfers 256 bytes at up to 100 khz) fast mode (transfers 256 bytes at up to 400 khz) transfer error detection and handling 3 interrupt flags per addr ess for maximum flexibility two interrupt request lines (one for slaves 1 and 2, the other for slave 3) full emulation of standard i 2 c eeproms: ? supports 5 read/write commands and combined format ?no i 2 c clock stretching ? programmable page size (8/16 bytes) or full buffer ? configurable write protection data integrity and byte-pair coherency when reading 16-bit words from i 2 c bus
on-chip peripherals st72344xx st72345xx 168/247 doc id 12321 rev 5 figure 71. i 2 c3s interface block diagram 11.7.3 general description in addition to receiving and transmitting data, i2 c3s converts it from serial to parallel format and vice versa. the interrupts are enabled or disabled by software. the i2c3s is connected to the i 2 c bus by a data pin (sda) and by a clock pin (scl). it can be connected both with a standard i 2 c bus and a fast i 2 c bus. the interface operates only in slave mode as transmitter/receiver. in order to fully emulate standard i 2 c eeprom devices with highest transfer speed, the peripheral prevents i 2 c clock signal stretching and performs data transfer between the shift register and the ram buffers using dma. communication flow a serial data transfer normally begins with a start condition and ends with a stop condition. both start and stop conditions are generated by an external master. refer to figure 67 for the standard protocol. the i2c3s is not a master and is not capable of generating a start/stop condition on the sda line. the i2c3s is capable of recognizing 3 slave addresses which are user programmable. the three i 2 c slave addresses can be individually enabled/disabled by software. since the i2c3s interface always acts as a slave it does not generate a clock. data and addresses are transferred as 8-bit bytes, msb first. the first byte following the start condition contains the slave address. a 9th clock pulse follows the 8 clock cycles of a byte transfer, during which the receiver must send an acknowledge bit to the transmitter. i 2 c slave address 1 i 2 c slave address 2 i 2 c slave address 3 cpu data/address bus ram 128 bytes slave 3 buffer 256 bytes slave 1 buffer 256 bytes slave 2 buffer dma comparator control logic 8-bit shift register scl or scli sda or sdai slave 1 or 2 interrupt slave 3 interrupt data e 2 prom 256 bytes register shadow
st72344xx st72345xx on-chip peripherals doc id 12321 rev 5 169/247 sda/scl line control when the i2c3s interface is enabled, the sda and scl ports must be configured as floating inputs. in this case, the value of the external pull-up resistor used depends on the application. when the i2c3s interface is disabled, the sda and scl ports revert to being standard i/o port pins. figure 72. i 2 c bus protocol 11.7.4 functional description the three slave addresses 1, 2 and 3 can be used as general purpose i 2 c slaves. they also support all features of standard i 2 c eeproms like the st m24cxx family and are able to fully emulate them. slaves 1 and 2 are mapped on the same interrupt vector. slave 3 has a separate interrupt vector with higher priority. the three slave addresses are defined by writing the 7 msbs of the address in the i2c3ssar1, i2c3ssar2 and i2c3 ssar3 registers. the slaves are enabled by setting the enable bits in the same registers. each slave has its own ram buffer at a fixed location in the st7 ram area. slaves 1 and 2 have 256-byte buffers which can be individually protected from i 2 c master write accesses. slave 3 has a 128-byte ram buffer without write protection feature. all three slaves have individual read flags (rf) and write flags (wf) with maskable interrupts. these flags are set when the i 2 c master has completed a read or write operation. paged operation to allow emulation of standard i 2 c eeprom devices, pages can be defined in the ram buffer. the pages are configured using the pl[1:0] bits in the i2c3scr1 register. 8/16-byte page length has to be selected depending on the eeprom device to emulate. the full page option is to be used when no paging of the ram buffer is required. the configuration is common to the 3 slave addresses. the full page configuration corresponds to 256 bytes for address 1 and 2 and to 128 bytes for address 3. paging affects the handling of rollover when write operations are performed. in case the bottom of the page is reached, the write continues from the first address of the same page. page length does not affect read operations: rollover is done on the whole ram buffer whatever the configured page length. scl sda 12 8 9 msb ack stop start condition condition
on-chip peripherals st72344xx st72345xx 170/247 doc id 12321 rev 5 the byte count register is reset when it reaches 256 bytes, whatever the page length, for all slave addresses, including slave 3. dma the i 2 c slaves use a dma controller to write/read data to/from their ram buffer. a dma request is issued to the dma controller on reception of a byte or just before transmission of a byte. when a byte is written by dma in ram, the cp u is stalled for max. 2 cycles. when several bytes are transferred from the i2c bus to ram, the dma releases between each byte and the cpu resumes processing until the dma writes the next byte. ram buffer write protection by setting the wp1/wp2 bits in the i2c3scr2 register it is possible to protect the ram buffer of slaves 1/2 respectively against write access from the master. if a write operation is attempted, the slave address is acknowledged, the current address register is overwritten, data is also acknowledged but it is not written to the ram. both the current address and byte count registers are incremented as in normal operation. in case of write access to a write protected address, no interrupt is generated and the busyw bit in the i2c3scr2 register is not set. only write operations are disabled/enabled. read operations are not affected. byte-pair coherency for i 2 c read operations byte-pair coherency allows the i 2 c master to read a 16-bit word and ensures that it is not corrupted by a simultaneous cpu update. two mechanisms are implemented, covering the two possible cases: 1. cpu updates a word in ram after the first byte has been transferred to the i2c shift register from ram. in this case, the first byte read from ram would be the msb of the old word and 2nd byte would be the lsb of the new word. to prevent this corruption, the i2c3s uses dma to systematically read a 2-byte word when it receives a read command from the i 2 c master. the msb of the word should be at address 2n. using dma, the msb is moved from ram address 2n to the i2c shift register and the lsb from ram address 2n+1 moved to a shadow register in the i2c3s peripheral. the cpu is stalled for a maximum of 2 cycles during word transfer. in case only one byte is read, the unus ed content of the sh adow register will be automatically overwritten when a new read operation is performed. in case a second byte is read in the same i 2 c message (no stop or restart condition) the content of the shadow register is transferred to the shift register and transmitted to the master. this process continues until a stop or restart condition occurs. 2. i2c3s attempts to read a word while the cpu is updating the ram buffer. to prevent data corruption, the cpu must switch operation to word mode prior to updating a word in the ram buffer. word mode is enabled by software using the b/w bit in the i2c3scr2 register. in word mode, when the cpu writes the msb of a word to address 2n, it is stored in a shadow register rather than being actually writ ten in ram. when the cpu writes the second byte (the lsb) at ad dress 2n+1, it is directly written in ram. the next cycle after the write to address 2n+ 1, the msb is automatically written from the shadow register to ram address 2n. dma is disabled for a 1 cycle while the cpu is writing a word.
st72344xx st72345xx on-chip peripherals doc id 12321 rev 5 171/247 word mode is disabled by hardware after the word update is performed. it must be enabled before each word update by cpu. use the following procedure when the st7 writes a word in ram: 1. disable interrupts 2. enable word mode by setting the b/w and busyw bits in the i2c3scr2 register. busyw bit is set to 1 when modifying any bits in control register 2. writing a 1 to this bit does not actually modify busyw but prevents accidental clearing of the bit. 3. write byte 1 in an even address in ram. th e byte is not actually written in ram but in a shadow register. this address must be within the i2c ram buffer of slave addresses 1, 2 or 3. 4. write byte 2 in the next higher address in ram. this byte is act ually written in ram. during the next cycle, the shadow register co ntent is written in t he lower address. the dma request is disabled during this cycle. 5. byte mode resumes automatically afte r writing byte 2 and dma is re-enabled. 6. enable interrupts note: word mode does not guarantee byte-pair coherency of words written by the i2c master in ram and read by the st7. byte pair coherency in this case must be handled by software. figure 73. 16-bit word write operation flowchart sends address and write bit decodes i2c3sns address decodes r/w bit sets write flag sends write address sends 1 byte of data stop condition updates current address- issues dma request resets i2c3sns write flag halts execution resumes execution services i2c3sns interrupt reads i2c3sns status register register y n delays while cpu completes word write sets busyw in control - word mode? host st7 cpu st7 i2c3sns repeat ram start address depends on slave address byte-pair coherency ensured by setting word mode normal execution max 1 cycle writes one byte to ram max 1 cycle register + i2c3s disabled issues interrupt enables i2c3sns updates control register
on-chip peripherals st72344xx st72345xx 172/247 doc id 12321 rev 5 figure 74. 16-bit word read operation flowchart application note taking full advantage of its higher interrupt priority slave 3 can be used to allow the addressing master to send data bytes as commands to the st7. these commands can be decoded by the st7 software to perform various operations such as programming the data e2prom via iap (in-app lication programming). slave 3 writes the command byte and other data in the ram and generates an interrupt. the st7 then decodes the command and processes the data as decoded from the command byte. the st7 also writes a status byte in the ram which the addressing master can poll. 11.7.5 address handling as soon as a start condition is detected, the address is received from the sda line and sent to the shift register. then it is compared with the three addresses of the interface to decode which slave of the interface is being addressed. address not matched : the interface ignores it and waits for another start condition. sends address and read bit decodes i2c3sns address decodes r/w bit sets read flag sends read address receives byte 1 stop condition updates current address- issues dma request reads 1 word from ram releases dma resets read flag halts execution resumes execution services i2c3sns interrupt reads i2c3sns status register register y n y n shadow reg => shift reg receives byte 2 delays while cpu completes word write updates status + dma cntl word mode? stop? byte 1 => shift reg byte 2 => shadow reg host st7 cpu st7 i2c3sns repeat ram start address depends on slave address byte-pair coherency ensured by setting word mode + dma on words normal execution max 3 cycles
st72344xx st72345xx on-chip peripherals doc id 12321 rev 5 173/247 address matched : the interface generates in sequence the following: an acknowledge pulse depending on the lsb of the slave address sent by the master, slaves enter transmitter or receiver mode. send an interrupt to the cpu after completion of the read/write operation after detecting the stop/ restart condition on the sda line. note: the status register has to be read to clear the event flag associated with the interrupt an interrupt will be generated onl y if the interrupt enable bit is set in the control register slaves 1 and 2 have a common interrupt and the slave 3 has a separate interrupt. at the end of write operation, i2c3s is temporarily disabled by hardware by setting busyw bit in cr2. the byte count register, status register and current address register should be saved before resetting busyw bit. slave reception (write operations) byte write : the slave address is followed by an 8-bit byte address. upon receipt of this address an acknowledge is generated, address is moved into the current address register and the 8 bit data is clocked in. once the data is shifted in, a dma request is generated and the data is written in the ram. the addressin g device will terminate th e write sequence with a stop condition. refer to figure 76 page write : a page write is initiated in similar way to a byte write, but the addressing device does not send a stop condition after the first data byte. the page length is programmed using bits 7:6 (pl[1:0]) in the control register1. the current address register value is incremented by one every time a byte is written. when this address reaches the page bo undary, the next byte will be wr itten at the beginning of the same page. refer to figure 77 . slave transmission (read operations) current address read: the current address register maintains the last address accessed during the last read or write operation incremented by one. during this operation the i2c slave reads the data pointed by the current address register. refer to figure 78 . random read : random read requires a dummy byte write sequence to load in the byte address. the addressing device then generates restart condition and resends the device address similar to current address read with the read/write bit high. refer to figure 79 . some types of i2c masters perform a dummy write with a stop condition and then a current address read. in either case, the slave generates a dma request, sends an acknowledge and serially clocks out the data. when the memory address limit is reached the curr ent address will roll ov er and the random read will continue till the addressing master sends a stop condition. sequential read: sequential reads are initiated by either a current address read or a random address read. after the addressing master receives the data byte it responds with an acknowledge. as long as the slave receives an acknowledge it will continue to increment the current address register and clock out sequential data bytes.
on-chip peripherals st72344xx st72345xx 174/247 doc id 12321 rev 5 when the memory address limit is reache d the current address will roll over and the sequential read will continue till the addressing master sends a stop condition. refer to figure 81 combined format if a master wants to continue communication either with another slave or by changing the direction of transfer then the master would generate a restart and provide a different slave address or the same slave address with the r/w bit reversed. refer to figure 82 . rollover handling the ram buffer of each slave is divided into pages whose length is defined according to pl1:0 bits in i2c3scr1. rollover takes place in these pages as described below. in the case of page write, if the number of data bytes transmitted is more than the page length, the current address will roll over to the first byte of the current page and the previous data will be overwritten. this page size is configured using pl[1:0] bit in the i2c3scr1 register. in case of sequential read, if the current address register value reaches the memory address limit the address will roll over to the first address of the reserved area for the respective slave. there is no status flag to indicate the roll over. note: the reserved areas for slaves 1 and 2 have a limit of 256 bytes. the area for slave 3 is 128 bytes. the msb of the address is hardwired, the addressing master therefore needs to send only an 8 bit address. the page boundaries are defined based on page size configuration using pl[1:0] bit in the i2c3scr1 register. if an 8-byte page size is selected, the upper 5 bits of the ram address are fixed and the lower 3 bits are incremented. for example, if the page write starts at register address 0x0c, the write will follow the sequence 0x0c, 0x 0d, 0x0e, 0x0f, 0x08, 0x09, 0x0a, 0x0b. if a 16-byte page size is selected, the upper 4 bits of the ram address are fixed and the lower 4 bits are incremented. for example if the page write starts at register address 0x0c, the write will follow the sequence 0x0c, 0x 0d, 0x0e, 0x0f, 0x00, 0x01, etc. error conditions berr : detection of a stop or a start condition during a byte transfer. in this case, the berr bit is set by hardware with an interrupt if iter is set. during a stop condition, the interface discards the data, releases the lines and waits for another start condition. however, a berr on a start condition will re sult in the interface discarding the data and waiting for the next slave address on the bus. nack : detection of a non-acknowledge bit not followed by a stop condition. in this case, nack bit is set by hardware with an interrupt if iter is set.
st72344xx st72345xx on-chip peripherals doc id 12321 rev 5 175/247 figure 75. transfer sequencing legend: s = start, p = stop, a = ac knowledge, na = non-acknowledge, wf = wf event, wfx bit is set (with interrupt if itwex=1, after stop or restart conditions), cleared by reading the i2c3ssr register while no communication is ongoing. rf = rf event, rfx is set (with interrupt if itrex=1, after stop or restart conditions), cleared by reading the i2c3ssr register while no communication is ongoing. busyw = busyw flag in the i2c3cr2 register set, cleared by software writing 0. note: the i2c3s supports a repeated start (s r ) in place of a stop condition (p). figure 76. byte write figure 77. page write figure 78. current address read figure 79. random read (dummy write + restart + current address read) 7-bit slave receiver: 7-bit slave transmitter: s address a data1 a data2 a ..... datan a p wf busyw s address a data1 a data2 a ..... datan na p rf sa w ack start ack data ack stop ba sa w ack start data ba ack stop ack data ack sa start data nack stop rack start ack ack start sa r ack data nack stop w sa ba
on-chip peripherals st72344xx st72345xx 176/247 doc id 12321 rev 5 figure 80. random read (dummy write + stop + start + current address read) figure 81. sequential read figure 82. combined format for read legend: sa - slave address, ba - byte address, w: write, r: read 11.7.6 low-power modes start ack ack start sa r ack data nack stop w sa ba stop start ack ack ack data nack stop sa rdata data start sa r ack data nack restart sa r ack data nack stop table 68. mode description mode description wait no effect on i 2 c interface. i2c interrupts causes the device to exit from wait mode. halt i 2 c registers are frozen. in halt mode, the i 2 c interface is inactive and does not acknowledge data on the bus. the i 2 c interface resumes operation when the mcu is woken up by an interrupt with ?exit from halt mode? capability. active-halt i 2 c registers are frozen. in active halt mode, the i 2 c interface is inactive and does not acknowledge data on the bus. the i 2 c interface resumes operation when the mcu is woken up by an interrupt with ?exit from active-halt mode? capability.
st72344xx st72345xx on-chip peripherals doc id 12321 rev 5 177/247 11.7.7 interrupt generation figure 83. event flags and interrupt generation note: read/write interrupts are generated only after stop or restart conditions. figure 83 shows the conditions for the generation of the two interrupts. itre1/2 rf1 rf2 nack iter berr wf1 wf2 itwe1/2 interrupt 1 itwe3 nack iter berr itre3 interrupt 2 wf3 rf3 (slave address 1/2) (slave address 3) data status flag data status flag dummy write write protect restart stop data status flag data status flag data status flag restart: stop: stop condition on sda dummy write: true if no data is written in ram data status flag: actual interrupt is produced when this condition is true write protect: true for write operation and if slaves restart: restart condition on sda slaves 1 and 2. for slave 3 and for read operation write protect will always be 0) are write protected (since this is applicable for restart condition on sda table 69. interrupt events interrupt event flag enable control bit exit from wait exit from halt interrupt on write to slave 1 wf1 itwe1 yes no interrupt on write to slave 2 wf2 itwe1 yes no interrupt on write to slave 3 wf3 itwe2 yes no interrupt on read from slave 1, slave 2 or slave 3. rf1- rf3 itrex yes no errors berr, nack iter yes no
on-chip peripherals st72344xx st72345xx 178/247 doc id 12321 rev 5 11.7.8 register description i 2 c 3s control register 1 (i2c3scr1) reset value: 0000 0000 (00h) bits 7:6 = pl1:0 page length configuration this bit is set and cleared by software. it is also cleared by hardware when the interface is disabled (pe=0). bit 5 = reserved, must be kept at 0. bit 4 = iter berr / nack interrupt enable this bit is set and cleared by software. it is also cleared by hardware when the interface is disabled (pe=0). 0: berr / nack interrupt disabled 1: berr / nack interrupt enabled note: in case of error, if iter is enabled either interrupt 1 or 2 is generated depending on which slave flags the error (see figure 83 ). bit 3= itre3 interrupt enable on read from slave 3 this bit is set and cleared by software it is also cleared by hardware when interface is disabled (pe =0). 0: interrupt on read from slave 3 disabled 1: interrupt on read from slave 3 enabled bit 2 = itre1/2 interrupt enable on read from slave 1 or 2 this bit is set and cleared by software it is also cleared by hardware when interface is disabled (pe =0) 0: interrupt on read from slave 1 or 2 disabled 1: interrupt on read from slave 1 or 2 enabled 7 0 pl1 pl0 0 iter itre3 itre1/2 itwe3 itwe 1/2 read / write table 70. pl configuration pl1 pl0 page length 00 8 01 16 1 0 full page (256 bytes for slave 1 & 2, 128 bytes for slave 3) 11 na
st72344xx st72345xx on-chip peripherals doc id 12321 rev 5 179/247 bit 1= itwe3 interrupt enable on write to slave 3 this bit is set and cleared by software. it is also cleared by hardware when interface is disabled. 0: interrupt after write to slave 3 disabled 1: interrupt after write to slave 3 enabled bit 0 = itwe1/2 interrupt enable on write to slave 1 or 2 this bit is set and cleared by software. it is also cleared by hardware when interface is disabled software. it is also cleared by hardware when interface is disabled. 0: interrupt after write to slave 1 or 2 disabled 1: interrupt after write to slave 1 or 2 enabled i2c control register 2 (i2c3scr2) reset value: 0000 0000 (00h) bits 7:5 = reserved, must be kept at 0. bit 4 = wp2 write protect enable for slave 2 this bit is set and cleared by software. it is also cleared by hardware when the interface is disabled (pe=0) 0: write access to slave 2 ram buffer enabled 1: write access to slave 2 ram buffer disabled bit 3 = wp1 write protect enable for slave 1 this bit is set and cleared by software. it is also cleared by hardware when the interface is disabled (pe=0). 0: write access to slave 1 ram buffer enabled 1: write access to slave 1 ram buffer disabled note: (applicable for both wp2/ wp1) only write operations are disabled/enabled. read operations are not affected. if a write operation is attempted, the slave address is acknowledged, the current address register is overwritten, data is also acknowledged but it is not written to the ram. both the current address and byte count registers are incremented as in normal operation. no interrupt generated if slave is write protected busyw will not be set if sl ave is write protected bit 2 = pe peripheral enable this bit is set and cleared by software. 0: peripheral disabled 1: slave capability enabled note: to enable the i 2 c interface, write the cr register twice with pe=1 as the first write only activates the interface (only pe is set) 7 0 0 0 0 wp2 wp1 pe busyw b/w read / write
on-chip peripherals st72344xx st72345xx 180/247 doc id 12321 rev 5 bit 1 = busyw busy on write to ram buffer this bit is set by hardware when a stop/ restart is detected after a write operation. the i2c3s peripheral is temporarily disabled till th is bit is reset. this bit is cleared by software. if this bit is not cleared before the next slave address reception, further communication will be non-acknowle dged. this bit is set to 1 when modifying any bits in control register 2. writing a 1 to this bit does not actually modify busyw but prevents accidentally clearing of the bit. 0: no busyw event occurred 1: a stop/ restart is detected after a write operation bit 0 = b/w byte / word mode this control bit must be set by software before a word is updated in the ram buffer and cleared by hardware after completion of the word update. in word mode the cpu cannot be interrupted when it is modifying the lsb byte and msb byte of the word. this mode is to ensure the coherency of data stored as words. 0: byte mode 1: word mode note: when word mode is enabled, all interrupts should be masked while the word is being written in ram. i 2 c3s status register (i2c3ssr) reset value: 0000 0000 (00h) bit 7= nack non acknowledge not followed by stop this bit is set by hardware when a non acknowledge returned by the master is not followed by a stop or restart condition. it is cleared by software reading the sr register or by hardware when the interface is disabled (pe=0). 0: no nack error occurred 1: non acknowledge not followed by stop bit 6 = berr bus error this bit is set by hardware when the interface detects a misplaced start or stop condition. it is cleared by software reading sr register or by hardware when the interface is disabled (pe=0). the scl line is not held low while berr=1. 0: no misplaced start or stop condition 1: misplaced start or stop condition bit 5 = wf3 write operation to slave 3 this bit is set by hardware on reception of the direction bit in the i 2 c address byte for slave 3. this bit is cleared when the stat us register is read when there is no communication ongoing or when the peripheral is disabled (pe = 0) 0: no write operation to slave 3 1: write operation performed to slave 3 7 0 nack berr wf3 wf2 wf1 rf3 rf2 rf1 read only
st72344xx st72345xx on-chip peripherals doc id 12321 rev 5 181/247 bit 4 = wf2 write operation to slave 2 this bit is set by hardware on reception of the direction bit in the i 2 c address byte for slave 2. this bit is cleared when the stat us register is read when there is no communication ongoing or when the peripheral is disabled (pe = 0) 0: no write operation to slave 2 1: write operation performed to slave 2 bit 3 = wf1 write operation to slave 1 this bit is set by hardware on reception of the direction bit in the i 2 c address byte for slave 1. this bit is cleared by software when the status register is read when there is no communication ongoing or by hardware when the peripheral is disabled (pe = 0). 0: no write operation to slave 1 1: write operation performed to slave 1 bit 2 = rf3 read operation from slave 3 this bit is set by hardware on reception of the direction bit in the i 2 c address byte for slave 3. it is cleared by software reading the sr register when there is no communication ongoing. it is also cleared by hardware when the interface is disabled (pe=0). 0: no read operation from slave 3 1: read operation performed from slave 3 bit 1= rf2 read operation from slave 2 this bit is set by hardware on reception of the direction bit in the i 2 c address byte for slave 2. it is cleared by software reading the sr register when there is no communication ongoing. it is also cleared by hardware when the interface is disabled (pe=0). 0: no read operation from slave 2 1: read operation performed from slave 2 bit 0= rf1 read operation from slave 1 this bit is set by hardware on reception of the direction bit in the i 2 c address byte for slave 1. it is cleared by software reading sr register when there is no communication ongoing. it is also cleared by hardware when the interface is disabled (pe=0). 0: no read operation from slave 1 1: read operation performed from slave 1 i 2 c byte count register (i2c3sbcr) reset value: 0000 0000 (00h) bits 7:0 = nb [7:0] byte count register this register keeps a count of the number of bytes received or transmitted through any of the three addresses. this byte count is reset after reception by a slave address of a new transfer and is incremented after each byte is transferred. this register is not limited by the full page length. it is also cleared by hardware when interface is disabled (pe =0). 7 0 nb7 nb6 nb5 nb4 nb3 nb2 nb1 nb0 read only
on-chip peripherals st72344xx st72345xx 182/247 doc id 12321 rev 5 i2c slave 1 address register (i2c3ssar1) reset value: 0000 0000 (00h) bits 7:1 = addr[7:1] address of slave 1 this register contains the first 7 bits of slave 1 address (excluding the lsb) and is user programmable. it is also cleared by hardware when interface is disabled (pe =0). bit 0= en1 enable bit for slave address 1 this bit is used to enable/disable slave address 1. it is also cleared by hardware when interface is disabled (pe =0). 0: slave address 1 disabled 1: slave address 1 enabled i2c slave 2 address register (i2c3ssar2) reset value: 0000 0000 (00h) bits 7:1 = addr[7:1] address of slave 2 . this register contains the first 7 bits of slave 2 address (excluding the lsb) and is user programmable. it is also cleared by hardware when interface is disabled (pe =0). bit 0= en2 enable bit for slave address 2 this bit is used to enable/disable slave address 2. it is also cleared by hardware when interface is disabled (pe =0). 0: slave address 2 disabled 1: slave address 2 enabled i2c slave 3 address register (i2c3ssar3) reset value: 0000 0000 (00h) bit 7:1 = addr[7:1] address of slave 3 this register contains the first 7 bits of slave 3 address (excluding the lsb) and is user programmable. it is also cleared by hardware when interface is disabled (pe =0). bit 0= en3 enable bit for slave address 3 this bit is used to enable/disable slave address 3. it is also cleared by hardware when interface is disabled (pe =0). 0: slave address 3 disabled 1: slave address 3 enabled 7 0 addr7 addr6 addr5 addr4 addr3 addr2 addr1 en1 read / write 7 0 addr7 addr6 addr5 addr4 addr3 addr2 addr1 en2 read / write 7 0 addr7 addr6 addr5 addr4 addr3 addr2 addr1 en3 read / write
st72344xx st72345xx on-chip peripherals doc id 12321 rev 5 183/247 i2c slave 1 memory current address register (i2c3scar1) reset value: 0000 0000 (00h) bit 7:0 = ca[7:0] current address of slave 1 buffer this register contains the 8 bit offset of slave address 1 reserved area in ram. it is also cleared by hardware when interface is disabled (pe =0). i2c slave 2 memory current address register (i2c3scar2) reset value: 0000 0000 (00h) bit 7:0 = ca[7:0] current address of slave 2 buffer this register contains the 8-bit offset of slave address 2 reserved area in ram. it is also cleared by hardware when interface is disabled (pe =0). i2c slave 3 memory current address register (i2c3scar3) reset value: 0000 0000 (00h) bit 6:0 = ca[6:0] current address of slave 3 buffer this register contains the 8-bit offset of slave address 3 reserved area in ram. it is also cleared by hardware when interface is disabled (pe =0). note: slave address 3 can store only 128 bytes. for slave address 3, ca7 bit will remain 0. i.e. if the byte address sent is 0x80 then the current address register will hold the value 0x00 due to an overflow. 7 0 ca7 ca6 ca5 ca4 ca3 ca2 ca1 ca0 read only 7 0 ca7 ca6 ca5 ca4 ca3 ca2 ca1 ca0 read only 7 0 ca7 ca6 ca5 ca4 ca3 ca2 ca1 ca0 read only table 71. i 2 c3s register map address (hex.) register name 7654321 0 0060h i2c3scr1 pl1 pl0 0 iter itre3 itre1/2 itwe3 itwe1/2 0061h i2c3scr2 0 0 0 wp2 wp1 pe busyw b/w 0062h i2c3ssr nack berr wf3 wf2 wf1 rf3 rf2 rf1 0063h i2c3sbcr nb7 nb6 nb5 nb4 nb3 nb2 nb1 nb1 0064h i2c3ssar1 addr7 addr6 addr5 addr4 addr3 addr2 addr1 en1 0065h i2c3scar1 ca 7 .. ca0
on-chip peripherals st72344xx st72345xx 184/247 doc id 12321 rev 5 0066h i2c3ssar2 addr7 addr6 addr5 addr4 addr3 addr2 addr1 en2 0067h i2c3scar2 ca 7 .. ca0 0068h i2c3ssar3 addr7 addr6 addr5 addr4 addr3 addr2 addr1 en3 0069h i2c3scar3 ca 7 .. ca0 table 71. i 2 c3s register map (continued) address (hex.) register name 7654321 0
st72344xx st72345xx on-chip peripherals doc id 12321 rev 5 185/247 11.8 10-bit a/d converter (adc) 11.8.1 introduction the on-chip analog to digital converter (adc) peripheral is a 10-bit, successive approximation converter with internal sample and hold circuitry. this peripheral has up to 16 multiplexed analog input channels (refer to device pinout description) that allow the peripheral to convert the analog voltage levels from up to 16 different sources. the result of the conversion is stored in a 10-bit data register. the a/d converter is controlled through a control/status register. note: whenever you change the c hannel or write in the adccsr register, the adc conversion starts again. 11.8.2 main features 10-bit conversion up to 16 channels with multiplexed input linear successive approximation data register (dr) whic h contains the results conversion complete status flag on/off bit (to reduce consumption) the block diagram is shown in figure 84 . figure 84. adc block diagram ch2 ch1 eoc speed adon 0 ch0 adccsr ain0 ain1 analog to digital converter ainx analog mux d4 d3 d5 d9 d8 d7 d6 d2 adcdrh 4 div 4 f adc f cpu d1 d0 adcdrl 0 1 00 0000 ch3 div 2
on-chip peripherals st72344xx st72345xx 186/247 doc id 12321 rev 5 11.8.3 functional description the conversion is monotonic, meaning that the result never decreases if the analog input does not and never increases if the analog input does not. if the input voltage (v ain ) is greater than v aref (high-level voltage reference) then the conversion result is ffh in the adcdrh register and 03h in the adcdrl register (without overflow indication). if the input voltage (v ain ) is lower than v ssa (low-level voltage reference) then the conversion result in the adcdrh an d adcdrl registers is 00 00h. the a/d converter is linear and the digital result of the conv ersion is stored in the adcdrh and adcdrl registers. the accuracy of the conversion is described in the electrical characteristics section. r ain is the maximum recommended impedance for an analog input signal. if the impedance is too high, this will result in a loss of accuracy due to leakage and samp ling not being completed in the allotted time. a/d converter configuration the analog input ports must be configured as input, no pull-up, no interrupt. refer to the ?i/o ports? chapter. using these pins as analog inputs does not affect the ability of the port to be read as a logic input. in the adccsr register: ? select the cs[3:0] bits to assign the analog channel to convert. starting the conversion in the adccsr register: set the adon bit to enable the a/d converter and to start the conversion. from this time on, the adc performs a continuous conversion of the selected channel. when a conversion is complete: the eoc bit is set by hardware. the result is in the adcdr registers. a read to the adcdrh resets the eoc bit. to read the 10 bits, perform the following steps: 1. poll the eoc bit 2. read the adcdrl register 3. read the adcdrh register. th is clears eoc automatically. note: the data is not latched, so both the low and the high data register must be read before the next conversion is complete, so it is recommended to disable interrupts while reading the conversion result. to read only 8 bits, perform the following steps: 1. poll the eoc bit 2. read the adcdrh register. th is clears eoc automatically.
st72344xx st72345xx on-chip peripherals doc id 12321 rev 5 187/247 changing the conversion channel the application can change channels during conversion. when software modifies the ch[3:0] bits in the adccsr register, the cu rrent conversion is stopped, the eoc bit is cleared, and the a/d converter starts converting the newly selected channel. 11.8.4 low-power modes note: the a/d converter may be disabled by resetting the adon bit. this feature allows reduced power consumption when no conversion is needed. 11.8.5 interrupts none. 11.8.6 register description control/status register (adccsr) reset value: 0000 0000 (00h) bit 7 = eoc end of conversion this bit is set by hardware. it is cleared by hardware when software reads the adcdrh register or writes to any bit of the adccsr register. 0: conversion is not complete 1: conversion complete bit 6 = speed adc clock selection this bit is set and cleared by software. 0: f adc = f cpu /4 1: f adc = f cpu /2 bit 5 = adon a/d converter on this bit is set and cleared by software. 0: disable adc and stop conversion 1: enable adc and start conversion bit 4 = reserved. must be kept cleared. table 72. mode description mode description wait no effect on a/d converter halt a/d converter disabled. after wakeup from halt mode, the a/d converter requires a stabilization time t stab (see electrical characteristics) before accurate conversions can be performed. 7 0 eoc speed adon 0 ch3 ch2 ch1 ch0 read/write (except bit 7 read only)
on-chip peripherals st72344xx st72345xx 188/247 doc id 12321 rev 5 bits 3:0 = ch[3:0] channel selection these bits are set and cleared by software. they select the analog input to convert. data register (adcdrh) reset value: 0000 0000 (00h) bits 7:0 = d[9:2] msb of converted analog value data register (adcdrl) reset value: 0000 0000 (00h) bits7:2 = reserved. forced by hardware to 0. bits 1:0 = d[1:0] lsb of converted analog value table 73. channel selection channel pin (1) 1. the number of channels is device dependen t. refer to the devic e pinout description. ch3 ch2 ch1 ch0 ain0 0000 ain1 0001 ain2 0010 ain3 0011 ain4 0100 ain5 0101 reserved 0110 reserved 0111 ain8 1000 reserved 1001 ain10 1010 reserved 1011 ain12 1100 ain13 1101 ain14 1110 ain15 1111 7 0 d9 d8 d7 d6 d5 d4 d3 d2 read only 7 0 000000d1d0 read only
st72344xx st72345xx on-chip peripherals doc id 12321 rev 5 189/247 table 74. adc register map and reset values address (hex.) register label 76543210 0070h adccsr reset value eoc 0 speed 0 adon 00 ch3 0 ch2 0 ch1 0 ch0 0 0071h adcdrh reset value d9 0 d8 0 d7 0 d6 0 d5 0 d4 0 d3 0 d2 0 0072h adcdrl reset value000000 d1 0 d0 0
instruction set st72344xx st72345xx 190/247 doc id 12321 rev 5 12 instruction set 12.1 st7 addressing modes the st7 core features 17 different addressing modes which can be classified in seven main groups: the st7 instruction set is designed to minimize the number of bytes required per instruction: to do so, most of the addressing modes may be subdivided in two submodes called long and short: long addressing mode is more powerful because it can use the full 64 kbyte address space, however it uses more bytes and more cpu cycles. short addressing mode is less powerful because it can generally only access page zero (0000h - 00ffh range), but the instruction size is more compact, and faster. all memory to memory instructions use shor t addressing modes only (clr, cpl, neg, bset, bres, btjt, btjf, inc, dec, rlc, rrc, sll, srl, sra, swap) the st7 assembler optimizes the use of long and short addressing modes. table 75. addressing mode groups addressing mode example inherent nop immediate ld a,#$55 direct ld a,$55 indexed ld a,($55,x) indirect ld a,([$55],x) relative jrne loop bit operation bset byte,#5 table 76. st7 addressing mode overview mode syntax destination/ source pointer addres pointer size (hex.) length (bytes) inherent nop + 0 immedi ate ld a,#$55 + 1 short direct ld a,$10 00..ff + 1 long direct ld a,$1000 0000..ffff + 2 no offset direct indexed ld a,(x) 00..ff + 0 (with x register) + 1 (with y register) short direct indexed ld a,($10,x) 00..1fe + 1 long direct indexed ld a,($1000,x) 0000..ffff + 2 short indirect ld a,[$10] 00..ff 00..ff byte + 2 long indirect ld a,[$10.w] 0000..ffff 00..ff word + 2
st72344xx st72345xx instruction set doc id 12321 rev 5 191/247 12.1.1 inherent all inherent instructions consist of a single byte. the opcode fully specifies all the required information for the cpu to process the operation. short indirect indexed ld a,([$10],x) 00..1fe 00..ff byte + 2 long indirect indexed ld a,([$10.w],x) 0000..ffff 00..ff word + 2 relative direct jrne loop pc-128/pc+127 (1) + 1 relative indirect jrne [$10] pc-128/pc+127 (1) 00..ff byte + 2 bit direct bset $10,#7 00..ff + 1 bit indirect bset [$10],#7 00..ff 00..ff byte + 2 bit direct relative btjt $10,#7,skip 00..ff + 2 bit indirect relative btjt [$10 ],#7,skip 00..ff 00..ff byte + 3 1. at the time the instruction is executed, the program counter (pc) points to the instruction following jrxx. table 76. st7 addressing mode overview (continued) mode syntax destination/ source pointer addres pointer size (hex.) length (bytes) table 77. inherent instructions inherent instruction function nop no operation trap s/w interrupt wfi wait for interrupt (low-power mode) halt halt oscillator (lowest power mode) ret subroutine return iret interrupt subroutine return sim set interrupt mask rim reset interrupt mask scf set carry flag rcf reset carry flag rsp reset stack pointer ld load clr clear push/pop push/pop to/from the stack inc/dec increment/decrement tnz test negative or zero cpl, neg 1 or 2 complement mul byte multiplication
instruction set st72344xx st72345xx 192/247 doc id 12321 rev 5 12.1.2 immediate immediate instructions have 2 bytes, the first byte contains the opcode, the second byte contains the operand value. 12.1.3 direct in direct instructions, the operands are referenced by their memory address. the direct addressing mode consists of two submodes: direct (short) the address is a byte, thus requires only 1 by te after the opcode, but only allows 00 - ff addressing space. direct (long) the address is a word, thus allowing 64 kbyte addressing space, but requires 2 bytes after the opcode. 12.1.4 indexed (no offset, short, long) in this mode, the operand is referenced by its memory address, which is defined by the unsigned addition of an index register (x or y) with an offset. the indirect addressing mode consists of three submodes: sll, srl, sra, rlc, rrc shift and rotate operations swap swap nibbles table 77. inherent instructions (continued) inherent instruction function table 78. immediate instructions immediate instruction function ld load cp compare bcp bit compare and, or, xor logical operations adc, add, sub, sbc arithmetic operations
st72344xx st72345xx instruction set doc id 12321 rev 5 193/247 indexed (no offset) there is no offset (no extra byte after the opcode), and allows 00 - ff addressing space. indexed (short) the offset is a byte, thus requires only 1 byte after the opcode and allows 00 - 1fe addressing space. indexed (long) the offset is a word, thus allowing 64 kbyte addressing space and requires 2 bytes after the opcode. 12.1.5 indirect (short, long) the required data byte to do the operation is found by its memory address, located in memory (pointer). the pointer address follows the opcode. the indirect addressing mode consists of two submodes: indirect (short) the pointer address is a byte, the pointer size is a byte, thus allowing 00 - ff addressing space, and requires 1 byte after the opcode. indirect (long) the pointer address is a byte, the pointer size is a word, thus allowing 64 kbyte addressing space, and requires 1 byte after the opcode. 12.1.6 indirect i ndexed (short, long) this is a combination of indirect and short indexed addressing modes. the operand is referenced by its memory address, which is defined by the unsigned addition of an index register value (x or y) with a pointer value located in memory. the pointer address follows the opcode. the indirect indexed addressing mode consists of two submodes: indirect indexed (short) the pointer address is a byte, the pointer size is a byte, thus allowing 00 - 1fe addressing space, and requires 1 byte after the opcode. indirect indexed (long) the pointer address is a byte, the pointer size is a word, thus allowing 64 kbyte addressing space, and requires 1 byte after the opcode.
instruction set st72344xx st72345xx 194/247 doc id 12321 rev 5 12.1.7 relative mode (direct, indirect) this addressing mode is used to modify the pc register value by adding an 8-bit signed offset to it. the relative addressing mode consists of two submodes: relative (direct) the offset follows the opcode. relative (indirect) the offset is defined in memory, of which the address follows the opcode. table 79. instructions supporting direct, i ndexed, indirect and indirect indexed addressing modes long and short instructions function ld load cp compare and, or, xor logical operations adc, add, sub, sbc arithmetic addition/subtraction operations bcp bit compare table 80. short instructions short instructions only function clr clear inc, dec increment/decrement tnz test negative or zero cpl, neg 1 or 2 complement bset, bres bit operations btjt, btjf bit test and jump operations sll, srl, sra, rlc, rrc shift and rotate operations swap swap nibbles call, jp call or jump subroutine table 81. relative direct/indirect instructions available relative direct/i ndirect instructions function jrxx conditional jump callr call relative
st72344xx st72345xx instruction set doc id 12321 rev 5 195/247 12.2 instruction groups the st7 family devices use an instruction set consisting of 63 instructions. the instructions may be subdivided into 13 main groups as illustra ted in the following table: using a prebyte the instructions are described with 1 to 4 bytes. in order to extend the number of available opcodes for an 8-bit cpu (256 opcodes), three different prebyte opcodes are defined. these prebytes modify the meaning of the instruction they precede. the whole instruction becomes: pc-2 end of previous instruction pc-1 prebyte pc opcode pc+1 additional word (0 to 2) according to the number of bytes required to compute the effective address these prebytes enable instruction in y as well as indirect addressing modes to be implemented. they precede the opcode of the instruction in x or the instruction using direct addressing mode. the prebytes are: table 82. main instruction groups load and transfer ld clr stack operation push pop rsp increment/decrement inc dec compare and tests cp tnz bcp logical operations and or xor cpl neg bit operation bset bres conditional bit test and branch btjt btjf arithmetic operations adc add sub sbc mul shift and rotates sll srl sra rlc rrc swap sla unconditional jump or call jra jrt jrf jp call callr nop ret conditional branch jrxx interruption management trap wfi halt iret condition code flag modification sim rim scf rcf pdy 90 replace an x based instruction using immediate, direct, indexed, or inherent addressing mode by a y one. pix 92 replace an instruction using direct, direct bit or direct relative addressing mode to an instruction using the corresponding indirect addressing mode. it also changes an instruction using x indexed addressing mode to an instruction using indirect x indexed addressing mode. piy 91 replace an instruction using x indirect indexed addressing mode by a y one.
instruction set st72344xx st72345xx 196/247 doc id 12321 rev 5 12.2.1 illegal opcode reset in order to provide enhanced robustness to the device against unexpected behavior, a system of illegal opcode detection is implem ented. if a code to be executed does not correspond to any opcode or prebyte value, a reset is generated. this, combined with the watchdog, allows the detection and recovery from an unexpected fault or interference. note: a valid prebyte associated with a valid opcode forming an unauthorized combination does not generate a reset. table 83. illegal opcode detection mnemo description function/example dst src h i n z c adc add with carry a = a + m + c a m h n z c add addition a = a + m a m h n z c and logical and a = a . m a m n z bcp bit compare a, memory tst (a . m) a m n z bres bit reset bres byte, #3 m bset bit set bset byte, #3 m btjf jump if bit is false (0) btjf byte, #3, jmp1 m c btjt jump if bit is true (1) btjt byte, #3, jmp1 m c call call subroutine callr call subroutine relative clr clear reg, m 0 1 cp arithmetic compare tst(reg - m) reg m n z c cpl one complement a = ffh-a reg, m n z 1 dec decrement dec y reg, m n z halt halt 0 iret interrupt routine return pop cc, a, x, pc h i n z c inc increment inc x reg, m n z jp absolute jump jp [tbl.w] jra jump relative always jrt jump relative jrf never jump jrf * jrih jump if ext. interrupt = 1 jril jump if ext. interrupt = 0 jrh jump if h = 1 h = 1 ? jrnh jump if h = 0 h = 0 ?
st72344xx st72345xx instruction set doc id 12321 rev 5 197/247 jrm jump if i = 1 i = 1 ? jrnm jump if i = 0 i = 0 ? jrmi jump if n = 1 (minus) n = 1 ? jrpl jump if n = 0 (plus) n = 0 ? jreq jump if z = 1 (equal) z = 1 ? jrne jump if z = 0 (not equal) z = 0 ? jrc jump if c = 1 c = 1 ? jrnc jump if c = 0 c = 0 ? jrult jump if c = 1 unsigned < jruge jump if c = 0 jmp if unsigned >= jrugt jump if (c + z = 0) unsigned > jrule jump if (c + z = 1) unsigned <= ld load dst <= src reg, m m, reg n z mul multiply x,a = x * a a, x, y x, y, a 0 0 neg negate (2's compl) neg $10 reg, m n z c nop no operation or or operation a = a + m a m n z pop pop from the stack pop reg reg m pop cc cc m h i n z c push push onto the stack push y m reg, cc rcf reset carry flag c = 0 0 ret subroutine return rim enable interrupts i = 0 0 rlc rotate left true c c <= dst <= c reg, m n z c rrc rotate right true c c => dst => c reg, m n z c rsp reset stack pointer s = max allowed sbc subtract with carry a = a - m - c a m n z c scf set carry flag c = 1 1 sim disable interrupts i = 1 1 sla shift left arithmetic c <= dst <= 0 reg, m n z c sll shift left logic c <= dst <= 0 reg, m n z c srl shift right logic 0 => dst => c reg, m 0 z c sra shift right arithmetic dst7 => dst => c reg, m n z c table 83. illegal opcode detection (continued) mnemo description function/example dst src h i n z c
instruction set st72344xx st72345xx 198/247 doc id 12321 rev 5 sub subtraction a = a - m a m n z c swap swap nibbles dst[7..4] <=> dst[3..0] reg, m n z tnz test for neg & zero tnz lbl1 n z trap s/w trap s/w interrupt 1 wfi wait for interrupt 0 xor exclusive or a = a xor m a m n z table 83. illegal opcode detection (continued) mnemo description function/example dst src h i n z c
st72344xx st72345xx electrical characteristics doc id 12321 rev 5 199/247 13 electrical characteristics 13.1 parameter conditions unless otherwise specified, all voltages are referred to v ss . 13.1.1 minimum and maximum values unless otherwise specified the minimum and ma ximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at t a =25c and t a =t a max (given by the selected temperature range). data based on characterization results, desi gn simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean3 ). 13.1.2 typical values unless otherwise specified, typical data are based on t a = 25 c, v dd = 5 v (for the 4.5 v v dd 5.5 v voltage range) and v dd = 3.3 v (for the 3 v v dd 3.6 v voltage range). they are given only as design guidelines and are not tested. 13.1.3 typical curves unless otherwise specified, all typical curves are given only as design guidelines and are not tested. 13.1.4 loading capacitor the loading conditions used for pin parameter measurement are shown in figure 85 . figure 85. pin loading conditions c l st7 pin
electrical characteristics st72344xx st72345xx 200/247 doc id 12321 rev 5 13.1.5 pin input voltage the input voltage measurement on a pin of the device is described in figure 86 . figure 86. pin input voltage 13.2 absolute maximum ratings stresses above those listed as ?absolute ma ximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device under these conditions is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. v in st7 pin table 84. voltage characteristics symbol ratings maximum value unit v dd - v ss supply voltage 7.0 v v in input voltage on any pin (1)&(2) 1. directly connecting the reset and i/o pins to v dd or v ss could damage the device if an unintentional internal reset is generated or an unexpected change of the i/o configuration occurs (for example, due to a corrupted program counter). to guarantee safe operat ion, this connection has to be done through a pull-up or pull-down resist or (typical: 4.7 k for reset , 10 k for i/os). unused i/o pins must be tied in the same way to v dd or v ss according to their reset configuration. 2. i inj(pin) must never be exceeded. this is implicitly insured if v in maximum is respected. if v in maximum cannot be respected, the injection current must be limited externally to the i inj(pin) value. a positive injection is induced by v in >v dd while a negative injection is induced by v in st72344xx st72345xx electrical characteristics doc id 12321 rev 5 201/247 table 85. current characteristics symbol ratings maximum value unit i vdd total current into v dd power lines (source) (1) 1. all power (v dd ) and ground (v ss ) lines must always be connect ed to the external supply. 75 ma i vss total current out of v ss ground lines (sink) (1) 150 i io output current sunk by any standard i/o and control pin 20 output current sunk by any high sink i/o pin 40 output current source by any i/os and control pin - 25 i inj(pin) (2)(3) 2. i inj(pin) must never be exceeded. this is implicitly insured if v in maximum is respected. if v in maximum cannot be respected, the injection current must be limited externally to the i inj(pin) value. a positive injection is induced by v in >v dd while a negative injection is induced by v in electrical characteristics st72344xx st72345xx 202/247 doc id 12321 rev 5 13.3 operating conditions note: when the power supply is between 2.7 and 2.95 v (v it+(lvd) max), the device is either in the guaranteed functional area or in reset state, thus allowing deterministic application behavior. however the lvd may generate a reset below 2.95 v and the user should therefore not use the device below this level when the lvd is enabled. figure 87. f cpu maximum operating frequency versus v dd supply voltage table 87. general operating conditions (1) 1. t a = -40 to +85 c unless otherwise specified. symbol parameter co nditions min max unit v dd supply voltage f cpu = 8 mhz. max. 3.3 5.5 v f cpu = 4 mhz. max. 2.7 5.5 f osc external clock frequency 3.3 v v dd 5.5 v up to 16 mhz 2.7 v v dd < 3.3 v up to 8 table 88. lvd thresholds symbol parameter conditions (1) 1. t a = -40 to +85 c unles s otherwise specified. min typ max unit v it+(lvd) reset release threshold (v dd rise) high threshold med. threshold low threshold 3.85 3.24 2.60 4.20 3.56 2.88 4.61 3.90 3.14 v v it-(lvd) reset generation threshold (v dd fall) high threshold med. threshold low threshold 3.66 3.04 2.45 3.98 3.36 2.71 4.36 3.66 2.95 v hys(lvd) lvd voltage threshold hysteresis v it+(lvd) -v it-(lvd) 200 mv vt por v dd rise time rate 20 (2) 2. not tested in production, guaranteed by design 100 (2) ms/v t g(vdd) v dd glitches filtered by lvd 150 ns f cpu [mhz] supply voltage [v] 8 4 2 0 4.0 4.5 5.0 functionality not guaranteed in this area 5.5 3.6 functionality guaranteed in this area 3.3 2.7 caution: reset may be activated by lvd in this area
st72344xx st72345xx electrical characteristics doc id 12321 rev 5 203/247 the st7 internal clock can be supplied by an internal rc o scillator and pll (selectable by option byte). table 89. avd thresholds symbol parameter conditions (1) 1. t a = -40 to +85c unles s otherwise specified. min (2) 2. not tested in production, guar anteed by characterization. typ max (2) unit v it+(avd) 1=>0 avdf flag toggle threshold (v dd rise) high threshold med. threshold low threshold 4.15 3.64 3.00 4.50 3.96 3.28 4.91 4.30 3.54 v v it-(avd) 0=>1 avdf flag toggle threshold (v dd fall) high threshold med. threshold low threshold 3.96 3.44 2.85 4.28 3.76 3.11 4.66 4.06 3.35 v hys(avd) avd voltage threshold hysteresis v it+(avd) -v it-(avd) 200 mv v it- voltage drop between adv flag set and lvd reset activated v it-(avd) -v it-(lvd) 450 mv table 90. pll characteristics symbol parameter conditions min typ max unit f pllin pll input frequency (1) 1. guaranteed by design. v dd = 2.7 to 3.65 v pll option x4 selected 0.95 1 1.05 mhz v dd = 3.3 to 5.5 v pll option x8 selected 0.90 1 1.10 v dd(pll) pll operating range pll option x4 selected (2) 2. to obtain a x4 multiplication ratio in the range 3.3 to 5.5v, the div2en option bit must enabled. 2.7 3.65 v pll option x8 selected 3.3 5.5 t w(jit) pll jitter period f rc = 1 mhz 8 khz jit pll pll jitter ( f cpu /f cpu ) vdd = 3.0 v 3.0 % vdd = 5.0 v 1.6 i dd(pll) pll current consumption t a =25 c 600 a table 91. internal rc oscillator and pll symbol parameter conditions min typ max unit v dd(rc) internal rc oscillator operating voltage refer to operating range of v dd with t a, section table 87. on page 202 2.7 5.5 v v dd(x4pll) x4 pll operating voltage 2.7 5.5 v dd(x8pll) x8 pll operating voltage 3.3 5.5 t startup pll startup time 60 pll input clock (f pll ) cycles
electrical characteristics st72344xx st72345xx 204/247 doc id 12321 rev 5 13.4 internal rc oscillator characteristics figure 88. typical rc frequency vs. rccr table 92. internal rc oscillator characteristics symbol parameter conditions min typ max unit f rc internal rc oscillator frequency (1) rccr = ff (reset value), t a = 25 c, v dd =5v 625 khz rccr = rccr0 (2) , t a = 25 c, v dd = 5 v 1000 rccr = ff (reset value), t a = 25 c, v dd =3v 612 rccr = rccr1 (2) , t a = 25 c, v dd = 3 v 1000 acc rc accuracy of internal rc oscillator with rccr=rccr0 (2) t a = 25 c, v dd = 5 v -1 +1 % t a = 25 c, v dd = 4.5 to 5.5 v (3) -1 +1 % t a = 25 to +85 c, v dd = 5 v (3) -3 +3 % t a = 25 to +85 c, v dd = 4.5 to 5.5 v (3) -3.5 +3.5 % t a = -40 to +25 c, v dd = 4.5 to 5.5 v (3) -3 +7 % i dd(rc) rc oscillator current consumption t a = 25 c, v dd = 5 v 600 (3) a t su(rc) rc oscillator setup time t a = 25 c, v dd = 5 v 10 (2) s 1. if the rc oscillator clock is selected, to improve clock stability and frequency ac curacy, it is recommended to place a decoupling capacitor, typically 100 nf, between the v dd and v ss pins as close as possi ble to the st7 device. it is also recommended to perform the calibration on board. 2. see internal rc oscillator on page 45 3. expected results. data based on charac terization, not tested in production t ypical rc freq (mhz) = f(rccr) @ 25c 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 0 50 100 150 200 250 rccr (decimal) f cpu mhz rc @ 5v rc @ 3v
st72344xx st72345xx electrical characteristics doc id 12321 rev 5 205/247 13.5 supply current characteristics the following current consumption specified for the st7 functional operating modes over temperature range does not take into account the clock source current consumption. to get the total device consumption, the two current values must be added (except for halt mode for which the clock is stopped). table 93. supply current symbol parameter conditions (1) 1. t a = -40 to +85c unles s otherwise specified typ max unit i dd supply current in run mode v dd =5.5v f cpu = 8 mhz (2) 2. cpu running with memory access , all i/o pins in input mode with a static value at v dd or v ss (no load), all peripherals in reset state; clock input (osc1) driven by external square wave, lvd disabled. 8.5 13 ma supply current in wait mode f cpu = 8 mhz (3) 3. all i/o pins in input mode with a static value at v dd or v ss (no load), all peripherals in reset state; clock input (osc1) driven by exter nal square wave, lvd disabled. 3.7 6 supply current in slow mode f cpu = 250 khz (4) 4. slow mode selected with f cpu based on f osc divided by 32. all i/o pins in input mode with a static value at v dd or v ss (no load), all peripherals in reset state; cloc k input (osc1) driven by external square wave, lvd disabled. 4.1 7 supply current in slow-wait mode f cpu = 250 khz (5) 5. slow-wait mode selected with f cpu based on f osc divided by 32. all i/o pins in input mode with a static value at v dd or v ss (no load), all peripherals in reset state; cl ock input (osc1) driven by external square wave, lvd disabled. 2.2 3.5 supply current in halt mode (6) 6. all i/o pins in output mode with a static value at v ss (no load), lvd disabled. data based on characterization results, tested in production at v dd max and f cpu max. -40c t a +85 c 1 10 a supply current in awufh mode (7)(8) 7. all i/o pins in input mode with a static value at v dd or v ss (no load). data tested in production at v dd max. and f cpu max. 8. this consumption refers to t he halt period only and not the asso ciated run period which is software dependent. t a = +25 c 50 60 supply current in active-halt mode 6)(7) t a = +25 c 500 700
electrical characteristics st72344xx st72345xx 206/247 doc id 12321 rev 5 figure 89. typical i dd in run vs. f cpu 1. graph displays data beyond the normal operating range of 3 v - 5.5 v. figure 90. typical i dd in run at f cpu = 8 mhz 1. graph displays data beyond the normal operating range of 3 v - 5.5 v. figure 91. typical i dd in slow vs. f cpu 1. graph displays data beyond the normal operating range of 3 v - 5.5 v. 0 1 2 3 4 5 6 7 8 9 2 2.5 3 3.5 4 4.5 5 5.5 6 6.5 vdd (v) idd run (ma) vs freq (mhz) .5 1 2 4 6 8 0 1 2 3 4 5 6 7 8 9 22.533.544.555.566.5 vdd (v) idd run (ma) at fcpu=8mhz 140c 90c 25c -5c -45c 0.00 0.10 0.20 0.30 0.40 0.50 0.60 0.70 0.80 0.90 6 5 4 3.3 2.7 vdd (v) idd (ma) 250khz 125khz 62khz
st72344xx st72345xx electrical characteristics doc id 12321 rev 5 207/247 figure 92. typical i dd in wait vs. f cpu 1. graph displays data beyond the normal operating range of 3 v - 5.5 v. figure 93. typical i dd in wait at f cpu = 8 mhz 1. graph displays data beyond the normal operating range of 3 v - 5.5 v. figure 94. typical i dd in slow-wait vs. f cpu 1. graph displays data beyond the normal operating range of 3 v - 5.5 v. 0 0.5 1 1.5 2 2.5 3 3.5 4 2 2.5 3 3.5 4 4.5 5 5.5 6 6.5 vdd (v) idd wfi (ma) vs fcpu (mhz) 0.5 1 2 4 6 8 0 0.5 1 1.5 2 2.5 3 3.5 4 22.533.544.555.566.5 vdd (v) idd wfi (ma) vs fcpu (mhz) 0.5 1 2 4 6 8 0.00 0.10 0.20 0.30 0.40 0.50 0.60 6 5 4 3.3 2.7 vdd (v) idd (ma) 250khz 125khz 62khz
electrical characteristics st72344xx st72345xx 208/247 doc id 12321 rev 5 figure 95. typical i dd vs. temp. at v dd = 5 v and f cpu = 8 mhz table 94. on-chip peripherals symbol parameter conditions typ unit i dd(16-bit timer) 16-bit timer supply current (1) 1. data based on a differential i dd measurement between reset confi guration (timer stopped) and a timer running in pwm mode at f cpu =8 mhz. f cpu = 4 mhz v dd = 3.0 v 20 a f cpu = 8 mhz v dd = 5.0 v 100 i dd(spi) spi supply current (2) 2. data based on a differential i dd measurement between reset configuration and a permanent spi master communication (data sent equal to 55h). f cpu = 4 mhz v dd = 3.0 v 250 f cpu = 8 mhz v dd = 5.0 v 800 i dd(adc) adc supply current when converting (3) 3. data based on a differential i dd measurement between reset configuration and continuous a/d conversions. f adc = 2 mhz v dd = 3.0 v 300 f adc = 4 mhz v dd = 5.0 v 1000 i dd(i2c) i2c supply current (4) 4. data based on a differential i dd measurement between reset conf iguration (i2c disabled) and a permanent i2c master communication at 100 khz (dat a sent equal to 55h). this measurement include the pad toggling consumption (4.7 k external pull-up on clock and data lines). f cpu = 4 mhz v dd = 3.0 v 100 f cpu = 8 mhz v dd = 5.0 v 500 i dd(sci) sci supply current (5) 5. data based on a differential i dd measurement between sci low power state (scid=1) and a permanent sci data transmit sequence. f cpu = 4 mhz v dd = 3.0 v 250 f cpu = 8 mhz v dd = 5.0 v 800 0.00 1.00 2.00 3.00 4.00 5.00 6.00 -45 25 90 110 temperature (c) idd (ma) run wait slow slow-wait
st72344xx st72345xx electrical characteristics doc id 12321 rev 5 209/247 13.6 clock and timing characteristics subject to general operating conditions for v dd , f osc , and t a . figure 96. typical application with an external clock source table 95. general timings symbol parameter (1) 1. guaranteed by design. not tested in production. conditions min typ (2) 2. data based on typical application software. max unit t c(inst) instruction cycle time f cpu =8 mhz 2312t cpu 250 375 1500 ns t v(it) interrupt reaction time (3) t v(it) = t c(inst) + 10 3. time measured between interrupt event and interrupt vector fetch. dtc(inst) is the number of t cpu cycles needed to finish the current instruction execution. f cpu =8 mhz 10 22 t cpu 1.25 2.75 s table 96. external clock source symbol parameter conditions min max unit v osc1h osc1 input pin high level voltage see figure 96 0.7xv dd v dd v v osc1l osc1 input pin low level voltage v ss 0.3xv dd t w(osc1h) t w(osc1l) osc1 high or low time (1) 1. data based on design simulation and/or technology characteristics, not tested in production. 15 ns t r(osc1) t f(osc1) osc1 rise or fall time (1) 15 i l oscx input leakage current v ss v in v dd 1 a osc1 osc2 f osc external st72xxx clock source not connected internally v osc1l v osc1h t r(osc1) t f(osc1) t w(osc1h) t w(osc1l) i l 90% 10%
electrical characteristics st72344xx st72345xx 210/247 doc id 12321 rev 5 13.6.1 crystal and ceramic resonator oscillators the st7 internal clock can be supplied with four different crystal/ceramic resonator oscillators. all the information given in this pa ragraph is based on characterization results with specified typical external components. in the application, the resonator and the load capacitors have to be placed as close as possibl e to the oscillator pins in order to minimize output distortion and startup stabilization time. refer to the crystal/ceramic resonator manufacturer for more details (frequency, package, accuracy, etc.). table 97. auto-wakeup from halt oscillator (awu) characteristics symbol parameter conditions min typ max unit f awu awu oscillator frequency 50 125 250 khz t rcsrt awu oscillator startup time 50 s table 98. crystal/ceramic resonator oscillator characteristics symbol parameter conditions min max unit f osc oscillator frequency (1) 1. the oscillator selection can be optimized in terms of supply current using an hi gh quality resonator with small r s value. refer to crystal/ceramic re sonator manufacturer for more details. 116mhz r f feedback resistor (2) 2. data based on characterisation results, not tested in production. the relatively low value of the rf resistor, offers a good protection against issues resu lting from use in a humid environment, due to the induced leakage and the bias condition change. however, it is recommended to take this point into account if the c is used in tough humidity conditions. 20 40 k c l1 c l2 recommended load capacitance versus equivalent serial resistance of the crystal or ceramic resonator (r s ) (3) 3. for c l1 and c l2 it is recommended to use high-quality ceramic c apacitors in the 5-pf to 25-pf range (typ.) designed for high-frequency applications and selected to match th e requirements of the crystal or resonator. c l1 and c l2, are usually the same size. the crystal manufacturer typica lly specifies a load capacitance which is the se ries combination of c l1 and c l2 . pcb and mcu pin capacitance must be included when sizing c l1 and c l2 (10 pf can be used as a rough estimate of the combined pin and board capacitance). see ta b l e 9 9 below pf i 2 osc2 driving current f osc = 2 mhz, c0 = 6 pf, cl1 = cl2 = 68 pf 426 a f osc = 4 mhz, c0 = 6 pf, cl1 = cl2 = 68 pf 425 f osc = 8 mhz, c0 = 6 pf, cl1 = cl2 = 40 pf 456 f osc = 16 mhz, c0 = 7 pf, cl1 = cl2 = 20 pf 660
st72344xx st72345xx electrical characteristics doc id 12321 rev 5 211/247 figure 97. typical application with a crystal or ceramic resonator table 99. recommended load capacitance vs. equivalent serial resistance of ceramic resonator supplier f osc [mhz] typical ceramic resonators (1) cl1 (2) [pf] cl2 (2) [pf] rf [ ] rd [ ] supply voltage range (v) temperature range (c) type (3) reference murata 2 smd cstcc2m00g56z-r0 (47) (47) open 0 2.7 to 5.5 ?40 c to 85 c 4 smd cstcr4m00g55z-r0 (39) (39) open 0 lead cstls4m00g56z-b0 (47) (47) open 0 8 smd cstce8m00g52z-r0 (10) (10) open 0 lead cstls8m00g53z-b0 (15) (15) open 0 16 smd cstce16m0v51z-r0 (5) (5) open 0 3.3 to 5.5 lead cstls16m0x53z-b0 (15) (15) 6.8 k 0 3.4 to 5.5 1. resonator characteristic s given by the ceramic resonator manufacturer. fo r more information on these resonators, please consult murata?s web site. 2. () means load capacitor built in resonator. 3. smd = [-r0: plastic tape pack age (? =180mm), -b0: bulk] lead = [-b0: bulk]. osc2 osc1 f osc c l1 c l2 i 2 r f st72xxx resonator when resonator with integrated capacitors v dd /2 ref power down logic feedback loop linear amplifier
electrical characteristics st72344xx st72345xx 212/247 doc id 12321 rev 5 13.7 memory characteristics t a = ?40c to 85c, unless otherwise specified. table 100. ram and hardware registers symbol parameter conditions min typ max unit v rm data retention mode (1) 1. minimum v dd supply voltage without losing data stored in ram (in halt mode or under reset) or in hardware registers ( only in halt mode). guaranteed by c onstruction, not tested in production. halt mode (or reset) 1.6 v table 101. flash program memory symbol parameter cond itions min typ max unit v dd operating voltage for flash write/erase refer to operating range of v dd with t a, table 87 on page 202 2.7 5.5 v t prog programming time for 1~32 bytes (1) 1. up to 32 bytes can be programmed at a time. t a =? 40 to +85c 5 10 ms t ret data retention (2) 2. data based on reliability test results and monitored in production. t a = +55c (3) 3. the data retention time increases when the t a decreases. 20 years n rw write erase cycles t a = +25c 10k (4) 4. design target value pending full product characterization. cycles i dd supply current (5) 5. guaranteed by design. not tested in production. read / write / erase modes f cpu = 8 mhz, v dd = 5.5v 2.6 ma no read/no write mode 100 a power down mode / halt 0 0.1 a table 102. eeprom data memory symbol parameter conditions min typ max unit v dd operating voltage for eeprom write/erase refer to operating range of v dd with t a, ta b l e 8 7 : general operating conditions on page 202 2.7 5.5 v t prog programming time for 1~32 bytes t a =? 40 to +85c 5 10 ms t ret data retention (1) 1. data based on reliability test results and monitored in production. t a =+55c (2) 2. the data retention time increases when the t a decreases. 20 years n rw write erase cycles t a = +25c 300k (3) 3. design target value pending full product characterization. cycles
st72344xx st72345xx electrical characteristics doc id 12321 rev 5 213/247 13.8 emc characteristics susceptibility tests ar e performed on a sample basis du ring product characterization. 13.8.1 functional ems (elect romagnetic susceptibility) based on a simple running application on the product (toggling 2 leds through i/o ports), the product is stressed by two electro magnetic ev ents until a failure occurs (indicated by the leds). esd : electro-static discharge (positive and negative) is applied on all pins of the device until a functional disturbance occurs. this test conforms with the iec 1000-4-2 standard. ftb : a burst of fast transient voltage (positive and negative) is applied to v dd and v ss through a 100 pf capacitor, until a functional disturbance occurs. this test conforms with the iec 1000-4-4 standard. a device reset allows normal operations to be resumed. the test results are given in the table below based on the ems levels and classes defined in application note an1709. designing hardened software to avoid noise problems emc characterization and optimization are performed at component level with a typical application environment and simplified mcu software. it should be noted that good emc performance is highly dependent on the user application and the software in particular. therefore it is recommended that the user applies emc software optimization and prequalification tests in relation with the emc level requested for his application. software recommendations: the software flowchart must include the management of runaway conditions such as: corrupted program counter unexpected reset critical data corruption (control registers...) prequalification trials: most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forc ing a low state on the reset pin or the oscillator pins for 1 second. to complete these trials, esd stress can be applied directly on the device, over the range of specification values. when unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note an1015). table 103. ems test results symbol parameter conditions level/ class v fesd voltage limits to be applied on any i/o pin to induce a functional disturbance v dd = 5 v, t a = +25 c, f osc = 8mhz conforms to iec 1000-4-2 tbd v fftb fast transient voltage burst limits to be applied through 100 pf on v dd and v dd pins to induce a functional disturbance v dd = 5 v, t a = +25 c, f osc = 8mhz conforms to iec 1000-4-4 tbd
electrical characteristics st72344xx st72345xx 214/247 doc id 12321 rev 5 13.8.2 emi (electromagnetic interference) based on a simple application running on the product (toggling 2 leds through the i/o ports), the product is monitored in terms of emi ssion. this emission test is in line with the norm sae j 1752/3 which sp ecifies the board and the loading of each pin. 13.8.3 absolute maximum rati ngs (electrical sensitivity) based on two different tests (esd and lu) using specific measurement methods, the product is stressed in order to determine its per formance in terms of electrical sensitivity. for more details, refer to the application note an1181. electrostatic discharge (esd) electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. the sample size depends on the number of supply pins in the device (3 parts*(n+1) supply pin). human body model can be simulated. this test conforms to the jesd22-a114a/a115a standard. static latch-up (lu) two complementary static tests are required on 6 parts to assess the latch-up performance. a supply overvoltage (applied to each power supply pin) a current injection (applied to each input, output and configurable i/o pin) performed on each sample. this test conforms to the eia/jesd 78 ic latch-up standard. for more details, refer to the application note an1181. table 104. emi emissions (1) 1. data based on characterization results, not tested in production. symbol parameter conditions monitored frequency band max vs. [f osc /f cpu ] unit 8/4 mhz 16/8 mhz s emi peak level v dd = 5v, t a = +25c, so20 package, conforming to sae j 1752/3 0.1 mhz to 30 mhz tbd tbd dbv 30 mhz to 130 mhz tbd tbd 130 mhz to 1 ghz tbd tbd sae emi level tbd tbd - table 105. esd absolute maximum ratings symbol ratings conditions maximum value (1) 1. data based on characterization results, not tested in production. unit v esd(hbm) electrostatic discharge voltage (human body model) t a = +25 c >2000 v
st72344xx st72345xx electrical characteristics doc id 12321 rev 5 215/247 13.9 i/o port pin characteristics table 106. electrical sensitivities symbol parameter conditions class lu static latch-up class t a = +25c t a = +85c a a table 107. general characteristics (1) 1. subject to general oper ating conditions for v dd , f osc , and t a unless otherwise specified. symbol parameter conditions min typ max unit v il input low level voltage (4) v ss - 0.3 0.3xv dd v v ih input high level voltage (4) 0.7xv dd v dd + 0.3 v hys schmitt trigger voltage hysteresis (4) 400 mv i l input leakage current v ss v in v dd 1 a i s static current consumption induced by each floating input pin (2) 2. configuration not recommended, all unused pins must be kept at a fixed voltage: using the output mode of the i/o for example or an external pull-up or pull-down resistor (see figure 98 ). static peak current value taken at a fixed v in value, based on design simulation and technol ogy characteristics, not tested in production. this value depends on v dd and temperature values. floating input mode 400 r pu weak pull-up equivalent resistor (3) 3. the r pu pull-up equivalent resistor is based on a resistive transistor. v in = v ss v dd =5v 50 120 250 k v dd =3v 160 c io i/o pin capacitance 5 pf t f(io)out output high to low level fall time (4) 4. data based on validation/design results. c l =50 pf between 10% and 90% 25 ns t r(io)out output low to high level rise time (4) 25 t w(it)in external interrupt pulse time (5) 5. to generate an external interrupt, a minimum pulse wi dth has to be applied on an i/o port pin configured as an external interrupt source. 1t cpu
electrical characteristics st72344xx st72345xx 216/247 doc id 12321 rev 5 figure 98. two typical applications with unused i/o pin 1. i/o can be left unconnected if it is configured as output (0 or 1) by the software. this has the advantage of greater emc robustness and lower cost. caution: during normal operation the iccclk pin must be pulled-up, internally or externally (external pull-up of 10k mandatory in noisy environment). this is to avoid entering icc mode unexpectedly during a reset. 10k unused i/o port st7xxx 10k unused i/o port st7xxx v dd table 108. output driving current (1) 1. subject to general oper ating conditions for v dd , f cpu , and t a unless otherwise specified. symbol parameter conditions min max unit v ol (2) 2. the i io current sunk must always respect the absolute maximum rating specified in table 85: current characteristics and the sum of i io (i/o ports and control pins) must not exceed i vss . output low level voltage for a standard i/o pin when 8 pins are sunk at same time (see figure 101 ) v dd = 5 v i io = +5 ma 1.0 v i io = +2 ma 0.4 output low level voltage for a high sink i/o pin when 4 pins are sunk at same time (see figure 104 ) i io = +20 ma 1.3 i io = +8 ma 0.75 v oh (3) 3. the i io current sourced must always respect the absolute maximum rating specified in table 85: current characteristics and the sum of i io (i/o ports and control pins) must not exceed i vdd . output high level voltage for an i/o pin when 4 pins are sourced at same time (see figure 113 ) i io = -5 ma v dd -1.5 i io = -2 ma v dd -0.8 v ol (2)(4) 4. not tested in production, based on characterization results. output low level voltage for a standard i/o pin when 8 pins are sunk at same time (see figure 100 ) v dd = 3.3 v i io = +2 ma 0.7 output low level voltage for a high sink i/o pin when 4 pins are sunk at same time i io = +8 ma 0.5 v oh (3)(4) output high level voltage for an i/o pin when 4 pins are sourced at same time ( figure 111 ) i io = -2 ma v dd -0.8 v ol (2)(4) output low level voltage for a standard i/o pin when 8 pins are sunk at same time (see figure 102 ) v dd = 2.7 v i io = +2 ma 0.9 output low level voltage for a high sink i/o pin when 4 pins are sunk at same time i io = +8 ma 0.6 v oh (3)(4) output high level voltage for an i/o pin when 4 pins are sourced at same time (see figure 110 ) i io = -2 ma v dd -0.9
st72344xx st72345xx electrical characteristics doc id 12321 rev 5 217/247 figure 99. typical v ol at v dd = 2.4 v (std i/os) figure 100. typical v ol at v dd = 3 v (std i/os) figure 101. typical v ol at v dd = 5 v (std i/os) 0 200 400 600 800 1000 0246 iload (ma) vol (mv) at vdd=2.4 v(std) -45c 25c 90c 130c 0 200 400 600 800 1000 0246 iload (ma) vol (mv) at vdd=2.4 v(std) -45c 25c 90c 130c 0 200 400 600 800 1000 0246 iload (ma) vol (mv) at vdd= 5 v(std) -45c 25c 90c 130c
electrical characteristics st72344xx st72345xx 218/247 doc id 12321 rev 5 figure 102. typical v ol at v dd = 2.4 v (high-sink i/os) figure 103. typical v ol at v dd = 3 v (high-sink i/os) figure 104. typical v ol at v dd = 5 v (high-sink i/os) 0 200 400 600 800 1000 0 2 4 6 8 10 12 14 16 18 20 iload (ma) vol (mv) at vdd=2.4 v(hs) -45c 25c 90c 130c 0 200 400 600 800 1000 1200 02468101214161820 iload (ma) vol (mv) at vdd=3 v(hs) -45c 25c 90c 130c 0 100 200 300 400 500 600 700 0 2 4 6 8 101214161820 iload (ma) vol (mv) at vdd=5 v(hs) -45c 25c 90c 130c
st72344xx st72345xx electrical characteristics doc id 12321 rev 5 219/247 figure 105. typical v ol vs. v dd (std i/os, 2 ma) figure 106. typical v ol vs. v dd (std i/os, 6 ma) figure 107. typical v ol vs. v dd (hs i/os, i io = 8 ma) 0 200 400 600 800 1000 2.4 2.6 2.8 3 5 ilo (ma) vol (mv) at ilo=2ma (std) -45c 25c 90c 130c 0 100 200 300 400 500 2.5 3 3.5 4 5 ilo (ma) vdd -voh (mv) at ilo=6ma -45c 25c 90c 130c 0 200 400 600 800 1000 2.4 2.6 2.8 3 5 ilo (ma) vol(mv) at ilo=8ma (hs) -45c 25c 90c 130c
electrical characteristics st72344xx st72345xx 220/247 doc id 12321 rev 5 figure 108. typical v ol vs. v dd (hs i/os, i io = 2 ma) figure 109. typical v ol vs. v dd (hs i/os, i io = 12 ma) figure 110. typical v dd ? v oh at v dd = 2.4 v (std i/os) 0 40 80 120 160 200 2.5 3 3.5 4 5 ilo (ma) vdd -voh (mv) at ilo=2ma -45c 25c 90c 130c 0 200 400 600 800 1000 2.4 2.6 2.8 3 5 ilo (ma) vol(mv) at ilo=12ma (hs) -45c 25c 90c 130c 0 200 400 600 800 1000 1200 1400 0 -2 -4 -6 -8 -10 -12 -14 -16 -18 -20 iload (ma) vdd-voh (mv) at vdd=2.4 v -45c 25c 90c 130c
st72344xx st72345xx electrical characteristics doc id 12321 rev 5 221/247 figure 111. typical v dd ? v oh at v dd = 3 v (std i/os) figure 112. typical v dd ? v oh at v dd = 4 v (std) figure 113. typical v dd ? v oh at v dd = 5 v (std) 0 300 600 900 1200 1500 1800 0 -2-4-6-8-10-12-14-16-18-20 iload (ma) vdd-voh (mv) at vdd=3 v -45c 25c 90c 130c 0 100 200 300 400 500 600 700 800 900 1000 1100 1200 0 -2 -4 -6 -8 -10 -12 -14 -16 -18 -20 iload (ma) vdd-voh (mv) at vdd=4 v -45c 25c 90c 130c 0 100 200 300 400 500 600 700 800 900 1000 0 -2 -4 -6 -8 -10 -12 -14 -16 -18 -20 iload (ma) vdd-voh (mv) at vdd=5 v -45c 25c 90c 130c
electrical characteristics st72344xx st72345xx 222/247 doc id 12321 rev 5 figure 114. typical v dd ? v oh vs. v dd (high sink) 13.10 control pin characteristics 13.10.1 asynchronous reset pin t a = -40 c to 85 c, unless otherwise specified. 0 40 80 120 160 200 2.533.54 5 ilo (ma) vdd -voh (mv) at ilo=2ma -45c 25c 90c 130c 0 100 200 300 400 500 2.533.54 5 ilo (ma) vdd -voh (mv) at ilo=6ma -45c 25c 90c 130c table 109. asynchronous reset pin characteristics symbol parameter conditions min typ max unit v il input low level voltage v ss - 0.3 0.3v dd v v ih input high level voltage 0.7v dd v dd + 0.3 v hys schmitt trigger voltage hysteresis (1) 1. data based on characterization results, not tested in production. 2v v ol output low level voltage (2) 2. the i io current sunk must always respect the absolute maximum rating specified in table 85: current characteristics and the sum of i io (i/o ports and control pins) must not exceed i vss . v dd = 5 v i io = +5 ma 0.5 1.0 v i io = +2 ma 0.2 0.4 r on pull-up equivalent resistor (3)(1) 3. the r on pull-up equivalent resistor is based on a resi stive transistor. specified for voltages on reset pin between v ilmax and v dd v dd = 5 v 20 40 80 k v dd = 3 v 40 70 120 t w(rstl)out generated reset pulse duration internal reset sources 14 (1) 32 s t h(rstl)in external reset pulse hold time (4) 4. to guarantee the reset of the device, a minimum pulse has to be applied to the reset pin. all short pulses applied on reset pin with a duration below t h(rstl)in can be ignored. 12 (1) s t g(rstl)in filtered glitch duration 200 ns
st72344xx st72345xx electrical characteristics doc id 12321 rev 5 223/247 figure 115. reset pin protection when lvd is enabled (1)(2)(3)(4) 1. the reset network protects t he device against par asitic resets. - the output of the external reset circuit must have an open-drain output to drive the st7 reset pad. otherwise the device can be damaged when the st7 generates an internal reset (lvd or watchdog). - whatever the reset source is (int ernal or external), the user must ensure that the level on the reset pin can go below the v il max. level specified in section 13.10.1 on page 222 . otherwise the reset will not be taken into account internally. - because the reset circuit is designed to allow the internal reset to be output in the reset pin, the user must ensure that the current sunk on the reset pin is less than the absolute maximum value specified for i inj(reset) in table 85 on page 201 . 2. when the lvd is enabled, it is recommended not to c onnect a pull-up resistor or capacitor. a 10nf pull- down capacitor is required to filter noise on the reset line. 3. in case a capacitive power supply is used, it is recommended to connect a 1m pull-down resistor to the reset pin to discharge any residual volt age induced by the capacitive effect of the power supply (this will add 5a to the power consumption of the mcu). 4. tips when using the lvd: 1. check that all recommendations related to the reset circuit have been applied (see notes above) 2. check that the power supply is properly decoupl ed (100nf + 10f close to the mcu). refer to an1709 and an2017. if this cannot be done, it is recommended to put a 100nf + 1m pull-down on the reset pin. 3. the capacitors connected on the reset pin and also the power supply are key to avoid any startup marginality. in most cases, steps 1 and 2 above ar e sufficient for a robust so lution. otherwise: replace 10nf pull-down on the reset pin with a 5f to 20f capacitor.? 5. please refer to section 12.2.1: illegal opcode reset for more details on ill egal opcode reset conditions. figure 116. reset pin protection when lvd is disabled (1) 1. the reset network protects t he device against par asitic resets. - the output of the external reset circuit must have an open-drain output to drive the st7 reset pad. otherwise the device can be damaged when the st7 generates an internal reset (lvd or watchdog). - whatever the reset source is (int ernal or external), the user must ensure that the level on the reset pin can go below the v il max. level specified in section 13.10.1 on page 222 . otherwise the reset will not be taken into account internally. - because the reset circuit is designed to allow the internal reset to be output in the reset pin, the user must ensure that the current sunk on the reset pin is less than the absolute maximum value specified for i inj(reset) in table 85 on page 201 . 2. please refer to section 12.2.1: illegal opcode reset for more details on ill egal opcode reset conditions. st72xxx pulse generator filter r on v dd internal reset reset external required 1 m optional (note 3) watchdog lvd reset illegal opcode (5) 0.01 f external reset circuit user required st72xxx pulse generator filter r on v dd internal reset watchdog illegal opcode (2) 0.01 f
electrical characteristics st72344xx st72345xx 224/247 doc id 12321 rev 5 13.11 communication interface characteristics 13.11.1 i 2 c and i2c3sns interfaces subject to general operating conditions for v dd , f osc , and t a unless otherwise specified. refer to i/o port characteristics for more details on the input/output alternate function characteristics (sdai and scli). the st7 i 2 c and i2c3sns interfaces meet the electrical and timing requirements of the standard i 2 c communication protocol. t a = -40c to 85c, unless otherwise specified. the following table gives the values to be wr itten in the i2cccr register to obtain the required i 2 c scl line frequency. note: for speeds around 200 khz, achieved speed can have 5% tolerance, for other speed ranges, achieved speed can have 2% tolerance. the above variations depend on the accuracy of the external components used. table 110. i 2 c and i2c3sns interfaces characteristics symbol parameter conditions min max unit f scl i2c scl frequency f cpu =4 mhz to 8 mhz (1) , v dd = 2.7 v to 5.5 v 1. the i 2 c and i2c3sns interfaces will not functi on below the minimum clock speed of 4 mhz. 400 khz f scl3sns i2c3sns scl frequency (2) 2. not tested in production within the whole operating range. guaranteed by design/validation test results. 400 khz table 111. scl frequency table (multimaster i 2 c interface) (1) 1. r p = external pull-up resistance, f scl = i 2 c speed, na = not achievable. f scl i2cccr value f cpu = 4 mhz. f cpu = 8 mhz. v dd = 3.3 v v dd = 5 v v dd = 3.3 v v dd = 5 v r p =3.3k r p =4.7k r p =3.3k r p =4.7k r p =3.3k r p =4.7k r p =3.3k r p =4.7k 400 na na na na 84h 84h 84h 84h 300 na na na na 86h 86h 85h 87h 200 84h 84h 84h 84h 8ah 8ah 8bh 8ch 100 11h 10h 11h 11h 25h 24h 28h 28h 50 25h 24h 25h 26h 4bh 4ch 53h 54h 20 60h 5fh 60h 62h ffh ffh ffh ffh
st72344xx st72345xx electrical characteristics doc id 12321 rev 5 225/247 13.12 10-bit adc characteristics t a = -40 c to 85 c, unless otherwise specified figure 117. adc accura cy characteristics table 112. adc accuracy symbol parameter conditions (1)(2) 1. data based on characterization results over the whole temperature range. 2. adc accuracy vs. negative injection current: injecting negative current on any of the analog input pins may reduce the accuracy of the conversi on being performed on another analog input. the effect of negative injection current on robust pins is specified in section 13.10 on page 222 any positive injection current with in the limits specified for i inj(pin) and i inj(pin) in section 13.9 does not affect the adc accuracy. typ max (3) 3. data based on characterization results, monitored in production to guarantee 99.73% within max value from -40 c to +125 c ( 3 distribution limits). unit |e t | total unadjusted error f cpu = 8 mhz, f adc = 4 mhz r ain < 10 ?, v dd = 2.7 v to 5.5 v 48 lsb |e o | offset error -1 -2 |e g | gain error -2 -4 |e d | differential linearity error 3 6 e o e g 1lsb ideal 1lsb ideal v dd v ss ? 1024 ------------------------------- - = v in (lsb ideal ) (1) example of an actual transfer curve (2) the ideal transfer curve (3) end point correlation line e t =total unadjusted er ror: maximum deviation between the actual and the ideal transfer curves. e o =offset error: deviation between the first actual transition and the first ideal one. e g =gain error: deviation between the last ideal transition and the last actual one. e d =differential linearity error: maximum deviation between actual steps and the ideal one. e l =integral linearity error: maximum deviation between any actual transition and the end point correlation line. digital result adcdr 1023 1022 1021 5 4 3 2 1 0 7 6 1234567 1021 1022 1023 1024 (1) (2) e t e d e l (3) v dd v ss ai15169
electrical characteristics st72344xx st72345xx 226/247 doc id 12321 rev 5 subject to general operating condition for v dd , f osc , and t a unless otherwise specified. figure 118. typical a/d converter application note: 1 c parasitic represents the capacitance of the pcb (dependent on soldering and pcb layout quality) plus the pad capacitance (3 pf). a high c parasitic value will downgrade conversion accuracy. to remedy this, f adc should be reduced. 2 this graph shows that depending on the input signal variation (f ain ), c ain can be increased for stabilization time and decr eased to allow the use of a larger serial resistor (r ain) . table 113. adc characteristics symbol parameter conditions min typ (1) 1. unless otherwise specified, typical data are based on t a = 25 c and v dd -v ss = 5 v. they are given only as design guidelines and are not tested. max unit f adc adc clock frequency 0.4 4 mhz v ain conversion voltage range (2) 2. when v dda and v ssa pins are not available on the pinout, the adc refers to v dd and v ss. v ssa v dda v r ain external input resistor 10 (3) 3. any added external serial resistor will downgrade the adc accuracy (especially for resistance greater than 10 k ). data based on characterization results, not tested in production. k c adc internal sample and hold capacitor 6 pf t stab stabilization time after adc enable f cpu = 8 mhz, f adc = 4 mhz 0 (4) 4. the stabilization time of the ad converter is masked by the first t load . the first conversion after the enable is then always valid. s t adc conversion time (sample+hold) 3.5 ? sample capacitor loading time ? hold conversion time 4 10 1/f adc i adc analog part 1 ma digital part 0.2 ainx st72xxx v dd i l 1 a v t 0.6 v v t 0.6 v c adc 6 pf v ain r ain 10-bit a/d conversion 2 k (max) c ain
st72344xx st72345xx package characteristics doc id 12321 rev 5 227/247 14 package characteristics 14.1 ecopack in order to meet environmental requirements, st offers these devices in different grades of ecopack? packages, depending on their level of environmental compliance. ecopack? specifications, grade definitions and product status are available at: www.st.com. ecopack? is an st trademark. 14.2 package mechanical data figure 119. 32-pin low profile quad flat package (7 x 7 mm) outline 1. drawing is not to scale. h c l l1 b e a1 a2 a e e1 d d1
package characteristics st72344xx st72345xx 228/247 doc id 12321 rev 5 figure 120. 40-lead very thin fine pitch quad flat no-lead package outline 1. drawing is not to scale. table 114. 32-pin low profile quad flat package (7 x 7 mm) mechanical data dim. mm inches (1) 1. values in inches are converted from mm and rounded to 4 decimal digits. min typ max min typ max a 1.60 0.0630 a1 0.05 0.15 0.0020 0.0059 a2 1.35 1.40 1.45 0.0531 0.0551 0.0571 b 0.30 0.37 0.45 0.0118 0.0146 0.0177 c 0.09 0.20 0.0035 0.0079 d 9.00 0.3543 d1 7.00 0.2756 e 9.00 0.3543 e1 7.00 0.2756 e 0.80 0.0315 0 3.5 7 0 3.5 7 l 0.45 0.60 0.75 0.0177 0.0236 0.0295 l1 1.00 0.0394 n (number of pins) 32 seating plane a d2 1 2 pin #1 id type c radius d e a1 a3 a2 b e e2 l
st72344xx st72345xx package characteristics doc id 12321 rev 5 229/247 figure 121. 44-pin low profile quad flat package outline 1. drawing is not to scale. table 115. 40-lead very thin fine pitch quad flat no-lead package mechanical data dim. mm inches (1) 1. values in inches are converted from mm and rounded to 4 decimal digits. min typ max min typ max a 0.80 0.90 1.00 0.0315 0.0354 0.0394 a1 0.02 0.05 0.0008 0.0020 a2 0.65 1.00 0.0256 0.0394 a3 0.20 0.0079 b 0.18 0.25 0.30 0.0071 0.0098 0.0118 d 5.85 6.00 6.15 0.2303 0.2362 0.2421 d2 2.75 2.9 3.05 0.1083 0.1142 0.1201 e 5.85 6 6.15 0.2303 0.2362 0.2421 e2 2.75 2.9 3.05 0.1083 0.1142 0.1201 e0.50 0.0197 l 0.30 0.40 0.50 0.0118 0.0157 0.0197 n number of pins 40 a a2 a1 b e l1 l h c e e1 d d1
package characteristics st72344xx st72345xx 230/247 doc id 12321 rev 5 figure 122. 48-pin low profile quad flat package outline 1. drawing is not to scale. table 116. 44-pin low profile quad flat package mechanical data dim. mm inches (1) 1. values in inches are converted from mm and rounded to 4 decimal digits. min typ max min typ max a 1.60 0.0630 a1 0.05 0.15 0.0020 0.0059 a2 1.35 1.40 1.45 0.0531 0.0551 0.0571 b 0.30 0.37 0.45 0.0118 0.0146 0.0177 c 0.09 0.20 0.0035 0.0079 d 12.00 0.4724 d1 10.00 0.3937 e 12.00 0.4724 e1 10.00 0.3937 e 0.80 0.0315 0 3.5 7 0 3.5 7 l 0.45 0.60 0.75 0.0177 0.0236 0.0295 l1 1.00 0.0394 n number of pins 44 e e1 d d1 l1 l c e b a1 a2 a
st72344xx st72345xx package characteristics doc id 12321 rev 5 231/247 table 117. 48-pin low profile quad flat package mechanical data dim. mm inches (1) 1. values in inches are converted from mm and rounded to 4 decimal digits. min typ max min typ max a 1.60 0.0630 a1 0.05 0.15 0.0020 0.0059 a2 1.35 1.40 1.45 0.0531 0.0551 0.0571 b 0.17 0.22 0.27 0.0067 0.0087 0.0106 c 0.09 0.20 0.0035 0.0079 d 9.00 0.3543 d1 7.00 0.2756 e 9.00 0.3543 e1 7.00 0.2756 e 0.50 0.0197 0 3.5 7 0 3.5 7 l 0.45 0.60 0.75 0.0177 0.0236 0.0295 l1 1.00 0.0394 n number of pins 48 table 118. thermal characteristics symbol ratings value (1) 1. values given for a 4-layer board. p dmax computed for t a = 125 c. unit r thja package thermal resistance (junction to ambient) lqfp32 60 c/w lqfp44 54 lqfp48 73 t jmax maximum junction temperature (2) 2. the maximum chip-junction temperature is based on technology characteristics. 150 c p dmax power dissipation (3) 3. the maximum power dissipation is obtained from the formula p d = (t j -t a ) / r thja . the power dissipation of an application can be defined by the user with the formula: p d =p int +p port where p int is the chip internal power (i dd x v dd ) and p port is the port power dissipation depending on the ports used in the application. lqfp32 415 mw lqfp44 460 lqfp48 340
device configuration and ordering information st72344xx st72345xx 232/247 doc id 12321 rev 5 15 device configuration and ordering information each device is available for production in user programmable versions (flash). st72f34x flash devices are shipped to customers with a default content (ffh). this implies that flash devices have to be configured by the customer using the option bytes. 15.1 option bytes the four option bytes allow the hardware configuration of the microcontroller to be selected. the option bytes can be accessed only in programming mode (for example using a standard st7 programming tool). 15.1.1 option byte 0 opt7 = wdg halt watchdog reset on halt this option bit determines if a reset is generated when entering halt mode while the watchdog is active. 0: no reset generation when entering halt mode 1: reset generation when entering halt mode opt6 = wdg sw hardware or software watchdog this option bit selects the watchdog type. 0: hardware (watchdog always enabled) 1: software (watchdog to be enabled by software) opt5:4 = lvd[1:0] low voltage detection selection these option bits enable the lvd block with a selected threshold as shown in ta bl e 1 1 9 . opt3:2 = sec[1:0] sector 0 size definition these option bits indicate the size of sector 0 according to the following table. table 119. lvd threshold configuration configuration lvd1 lvd0 lv d o f f 11 highest voltage threshold ( 4.1v) 1 0 medium voltage threshold ( 3.5v) 0 1 lowest voltage threshold ( 2.8v) 0 0 table 120. size of sector 0 sector 0 size sec1 sec0 0.5k 00 1k 01
st72344xx st72345xx device configuration and ordering information doc id 12321 rev 5 233/247 opt1 = fmp_r read-out protection readout protection, when selected provides a protection against program memory content extraction and against write access to flash memory. erasing the option bytes when the fmp_r option is selected will cause the whole memory to be erased first and the device can be reprogrammed. refer to the st7 flash programming reference manual and section 4.5 on page 29 for more details 0: read-out protection off 1: read-out protection on opt0 = fmp_w flash write protection this option indicates if the flash program memory is write protected. warning: when this option is selected, the program memory (and the option bit itself) can never be erased or programmed again. 0: write protection off 1: write protection on 15.1.2 option byte 1 opt7 = rstc reset clock cycle selection this option bit selects the number of cp u cycles inserted during the reset phase and when exiting halt mode. for reso nator oscillators, it is advise d to select 4096 due to the long crystal stabilization time. 0: reset phase with 4096 cpu cycles 1: reset phase with 256 cpu cycles opt6:4 = oscrange[2:0] oscillator range when the internal rc oscillator is not se lected (option osc=1) , these option bits select the range of th e resonator oscillator cu rrent source or the external clock source. 2k 10 4k 11 option byte 0 option byte 1 7654321076543210 wdg halt wdg sw lv d 1 lv d 0 sec1 sec0 fmpr fmpw rstc oscrange 2:0 osc div2en pll x4x8 pll off default value 1111110011110111 table 120. size of sector 0 sector 0 size sec1 sec0
device configuration and ordering information st72344xx st72345xx 234/247 doc id 12321 rev 5 opt3 = osc rc oscillator selection 0: rc oscillator on 1: rc oscillator off opt2 = div2en pll divide by 2 enable 0: pll division by 2 enabled 1: pll division by 2 disabled note: div2en must be kept disabled when pllx4 is enabled. opt1 = pllx4x8 pll factor selection 0: pllx4 1: pllx8 opt0 = plloff pll disable 0: pll enabled 1: pll disabled (by-passed) these option bits must be configured as described in ta b l e 1 2 2 depending on the voltage range and the expected cpu frequency 15.1.3 option byte 2 note: opt7:0 = reserved. must be kept at 1. table 121. selection of the resonator oscillator range oscrange 210 typical frequency range with resonator lp 1~2 mhz 0 0 0 mp 2~4 mhz 0 0 1 ms 4~8 mhz 0 1 0 hs 8~16 mhz 0 1 1 reserved 1 0 0 external clock 101 110 111 table 122. list of valid option combinations targ et ratio v dd option bits div2 en pll off pll x4x8 x4 (1) 1. for a target ratio of x4 between 3.3v - 3.65v, this is the recommended configuration. 2.7 v - 3.65 v x 0 0 x4 3.3 v - 5.5 v 001 x8 101
st72344xx st72345xx device configuration and ordering information doc id 12321 rev 5 235/247 15.1.4 option byte 3 opt7:6 = pkg1:0 package selection these option bits select the package. opt5 = i2c3s i2c3sns selection 0: i2c3sns selected 1: i2c3sns not selected opt4:0 = reserved. must be kept at 1. table 123. package selection version selected package pkg 1 pkg 0 klqfp32 00 slqfp4401 clqfp481x table 124. option byte default values option byte 2 option byte 3 7654321076 5 43210 reserved pkg1 pkg0 i2c3s reserved default value 11111111xx x 11111
device configuration and ordering information st72344xx st72345xx 236/247 doc id 12321 rev 5 15.2 device ordering information figure 123. st7234x ordering information scheme for a list of available options (e.g. memory size, package) and orderable part numbers or for further information on any aspect of this device, please contact the nearest st sales office. 15.3 development tools development tools for the st7 microcontrollers include a complete range of hardware systems and software tools from stmicroelectronics and third-party tool suppliers. the range of tools includes solutions to help you evaluate microcontroller peripherals, develop and debug your application, and program your microcontrollers. 15.3.1 starter kits st offers complete, affordable starter kits . starter kits are complete, affordable hardware/software tool packages that include features and samples to help you quickly start developing your application. st72 f 34x k 2 t 6 tr product class st7 microcontroller memory size 2 = 8k 4 = 16k package t = lqfp example: version flash temperature range 6 = -40 ?c to 85 ?c shipping tr = tape and reel no character = tray sub-family 344, 345 no. of pins k = 32 pins s = 44 pins c = 48 pins ai15170
st72344xx st72345xx device configuration and ordering information doc id 12321 rev 5 237/247 15.3.2 development and debugging tools application development for st7 is supported by fully optimizing c compilers and the st7 assembler-linker toolchain, which are all seamlessly integrated in the st7 integrated development environments in order to facilit ate the debugging and fine-tuning of your application. the cosmic c comp iler is available in a free version that outputs up to 16kbytes of code. the range of hardware tools includes full-featured st7-emu3 series emulators and the low-cost rlink in-circuit debugger/programmer. these tools are supported by the st7 toolset from stmicroelectronics, which includes the stvd7 integrated development environment (ide) with high-level language debugger, editor, project manager and integrated programming interface. 15.3.3 programming tools during the development cycle, the st7-emu3 series emulators and the rlink provide in- circuit programming capability fo r programming the flash microc ontroller on your application board. st also provides a low-cost dedicated in-circuit programmer, the st7-stick , as well as st7 socket boards which provide all the sockets requ ired for programming any of the devices in a specific st7 sub-family on a platform that can be used with any tool with in- circuit programming capability for st7. for production programming of st7 devices, st?s third-party tool partners also provide a complete range of gang and automated programming solutions, which are ready to integrate into your production environment.
device configuration and ordering information st72344xx st72345xx 238/247 doc id 12321 rev 5 15.3.4 order codes for st 72f34x development tools for additional ordering codes for spare parts and accessories, refer to the online product selector at www.st.com/mcu. table 125. development tool order codes mcu starter kit emulator programming tool in-circuit debugger/ programmer dedicated programmer st72f344 st72f345 st72f34x- sk/rais (1) 1. usb connection to pc st7mdt40-emu3 stx-rlink (2) st7-stick (3)(4) 2. rlink with st7 tool set 3. add suffix /eu, /uk or /us for the power supply for your region 4. parallel port connection to pc st7sb20j/xx (3)(5) st7sb40-qp48/xx (3)(6) 5. only available for lqfp32 and lqfp44 packages 6. only available for lqfp48 package
st72344xx st72345xx known limitations doc id 12321 rev 5 239/247 16 known limitations 16.1 external interrupt missed to avoid any risk if generating a parasitic interrupt, the edge detector is automatically disabled for one clock cycle during an access to either ddr and or. any input signal edge during this period will not be detect ed and will not generate an interrupt. this case can typically occur if the application refreshes the port configuration registers at intervals during runtime. 16.1.1 workaround the workaround is based on software checking the level on the interrupt pin before and after writing to the pxor or pxddr registers. if there is a level change (depending on the sensitivity programmed for this pin) the interr upt routine is invoked us ing the call instruction with three extra push instructions before executing the interrupt routine (this is to make the call compatible with the iret instruction at the end of the interrupt service routine). but detection of the level change does not make sure that edge occurs during the critical 1 cycle duration and the interrupt has been missed. this may lead to occurrence of same interrupt twice (one hardware and another with software call). to avoid this, a semaphore is set to '1' before checking the level change. the semaphore is changed to level '0' inside the interrupt routine. when a level change is detected, the semaphore status is checked and if it is '1' this means that the last interrupt has been missed. in this case, the interrupt rout ine is invoked with the call instruction. there is another possible case i.e. if writing to pxor or pxddr is done with global interrupts disabled (interrupt mask bit set). in this case, the semaphore is changed to '1' when the level change is detected. detecting a missed interrupt is done after the global interrupts are enabled (interrupt mask bit reset) and by checking the status of the semaphore. if it is '1' this means that the last interrupt was missed and the interrupt routine is invoked with the call instruction. to implement the workaround, the following software sequence is to be followed for writing into the pxor/pxddr registers. the example is for port pf1 with falling edge interrupt sensitivity. the software sequence is given for both cases (global interrupt disabled/enabled). case 1: writing to pxor or pxddr wi th global interrupts enabled: ld a,#01 ld sema,a; set the semaphore to '1' ld a,pfdr and a,#02 ld x,a; store the level before writing to pxor/pxddr ld a,#$90 ld pfddr,a; write to pfddr ld a,#$ff ld pfor,a; write to pfor
known limitations st72344xx st72345xx 240/247 doc id 12321 rev 5 ld a,pfdr and a,#02 ld y,a; store the level after writing to pxor/pxddr ld a,x; check for falling edge cp a,#02 jrne out tnz y jrne out ld a,sema; check the semaphore status if edge is detected cp a,#01 jrne out call call_routine; call the interrupt routine out:ld a,#00 ld sema,a .call_routine; entry to call_routine push a push x push cc .ext1_rt; entry to interrupt routine ld a,#00 ld sema,a iret case 2: writing to pxor or pxddr with global interrupts disabled: sim; set the interrupt mask ld a,pfdr and a,#$02 ld x,a; store the level before writing to pxor/pxddr ld a,#$90 ld pfddr,a; write into pfddr ld a,#$ff ld pfor,a; write to pfor ld a,pfdr and a,#$02 ld y,a; store the level after writing to pxor/pxddr ld a,x; check for falling edge
st72344xx st72345xx known limitations doc id 12321 rev 5 241/247 cp a,#$02 jrne out tnz y jrne out ld a,#$01 ld sema,a; set the semaphore to '1' if edge is detected rim; reset the interrupt mask ld a,sema; check the semaphore status cp a,#$01 jrne out call call_routine; call the interrupt routine rim out: rim jp while_loop .call_routine; entry to call_routine push a push x push cc .ext1_rt; entry to interrupt routine ld a,#$00 ld sema,a iret 16.1.2 unexpected reset fetch if an interrupt request occurs while a ?pop cc? instruction is ex ecuted, the interrupt controller does not recognise the source of the interrupt and, by default, passes the reset vector address to the cpu. workaround to solve this issue, a ?pop cc? instruction must always be preceded by a ?sim? instruction. 16.2 clearing active interru pts outside interrupt routine when an active interrupt request occurs at the same time as the related flag is being cleared, an unwanted reset may occur. note: clearing the related interrupt mask will not generate an unwanted reset
known limitations st72344xx st72345xx 242/247 doc id 12321 rev 5 concurrent interrupt context the symptom does not occur when the interrupts are handled normally, i.e. when: the interrupt flag is cleared within its own interrupt routine the interrupt flag is cleared within any interrupt routine the interrupt flag is cleared in any part of the code while this interrupt is disabled if these conditions are not met, the symptom can be avoided by implementing the following sequence: perform sim and rim operation before and after resetting an active interrupt request. example: sim reset interrupt flag rim nested interrupt context: the symptom does not occur when the interrupts are handled normally, i.e. when: the interrupt flag is cleared within its own interrupt routine the interrupt flag is cleared within any interrupt routine with higher or identical priority level the interrupt flag is cleared in any part of the code while this interrupt is disabled if these conditions are not met, the symptom can be avoided by implementing the following sequence: push cc sim reset interrupt flag pop cc 16.3 16-bit timer pwm mode in pwm mode, the first pwm pulse is missed after writing the value fffch in the oc1r register (oc1hr, oc1lr). it leads to either full or no pwm during a period, depending on the olvl1 and olvl2 settings. 16.4 timd set simultaneously with oc interrupt if the 16-bit timer is disabled at the same time the output compare event occurs then output compare flag gets locked and cannot be cleared before the timer is enabled again. 16.4.1 impact on the application if output compare interrupt is enabled, then the output compare flag cannot be cleared in the timer interrupt routine. consequently the interrupt service routine is called repeatedly.
st72344xx st72345xx known limitations doc id 12321 rev 5 243/247 16.4.2 workaround disable the timer interrupt before disabling the timer. again while enabling, first enable the timer then the timer interrupts. perform the following to disable the timer: tacr1 = 0x00h; // disable the compare interrupt tacsr |= 0x40; // disable the timer perform the following to enable the timer again: tacsr &= ~0x40; // enable the timer tacr1 = 0x40; // enable the compare interrupt 16.5 sci wrong break duration 16.5.1 description a single break characte r is sent by setting and resetting the sbk bit in the scicr2 register. in some cases, the break character may have a longer duration than expected: 20 bits instead of 10 bits if m=0 22 bits instead of 11 bits if m=1 in the same way, as long as the sbk bit is se t, break characters are sent to the tdo pin. this may lead to generate one break more than expected. 16.5.2 occurrence the occurrence of the problem is random and proportional to the baudrate. with a transmit frequency of 19200 baud (f cpu =8 mhz and scibrr=0xc9), the wrong break duration occurrence is around 1%. 16.5.3 workaround if this wrong duration is not compliant with th e communication protocol in the application, software can request that an idle line be generated before the break character. in this case, the break duration is always correct assuming the application is not doing anything between the idle and the break. this can be ensured by temporarily disabling interrupts. the exact sequence is: disable interrupts reset and set te (idle request) set and reset sbk (break request) re-enable interrupts
known limitations st72344xx st72345xx 244/247 doc id 12321 rev 5 16.6 random read operations not supported with the standard i2c 16.6.1 description the standard i2c pe ripheral is not fully compliant with random read capabilities (only the i2c3sns interface supports these capabilities). if the master sends a restart condition, a bus error is generated on the st7 device in slave mode. 16.6.2 occurrence the occurrence of the problem is random. 16.6.3 workaround the restart condition is not allowed. the master must not send a restart condition. it must send a stop condition before a second start (each start has to be preceded by a stop). 16.7 programming of eeprom data 16.7.1 description in user mode, when programming eeprom da ta memory, the read access to the program memory between e000h and ffffh can be corrupted. 16.7.2 impact on application the eeprom programming routine must be loca ted outside this pr ogram memory area. any access to the interrupt vector table can result in an unexpected code being executed, so the interrupts must be masked. 16.7.3 workaround the sequence to program the eeprom data (refer to section 5.3 on page 31 ) must be executed within c000h-dfffh area or from the ram. it is as follows: set e2lat bit write up to 32 bytes in e2prom area sim ; to disable the interrupts set e2pgm bit wait for e2pgm=0 rim ; to enable the interrupts return to the program memory
st72344xx st72345xx revision history doc id 12321 rev 5 245/247 17 revision history table 126. document revision history date revision changes 29-april-2006 1 first release on internet 23-oct-2006 2 removed references to bga56 and qfn40 packages tqfp package naming changed to lqfp (low-profile quad flat) changed number of i/o ports on first page pdvd (power down voltage detector) replaced by avd (auxiliary voltage detector) modified note 3 to table 4 on page 24 added pf4 to figure 3 on page 18 and figure 4 on page 19 modified memory access on page 31 modified figure 8 , figure 9 on page 33 and figure 10 on page 34 changed rccr table in section 7.3 on page 43 (f rc =1 mhz) references to pdvdf, pdvdie corrected to avdf, avdie: section 7.6.2 on page 49 current characteristics table 85 on page 201 updated general operating conditions table updated, table 87 on page 202 data updated in table 88 on page 202 , note replaced table modified in table 89 on page 203 notes adjusted for table in table 90 on page 203 modified section 13.4 on page 204 (for v dd =5v) ta bl e i n table 93 on page 205 modified updated table 94 on page 208 added table 96 on page 209 and figure 96 on page 209 ta bl e i n table 101 on page 212 modified absolute maximum ratings and electrical sensitivity table updated, section 13.8.3 on page 214 added note 1 to v il and v ih in table 107 on page 215 ta bl e i n table 108 on page 216 modified (for v dd = 3.3v and v dd =2.7v) modified graphs in table 108 on page 216 t g(rstl)in updated in table 13.10 on page 222 updated table 111 on page 224 updated table 118 on page 231 modified default values for option byte 2 and 3 on option byte 2 on page 234 added option list on option byte 2 on page 234 added section 15.3: development tools on page 236 added known limitations: section 16.6: in-application programming on page 242 , section 16.7: programming of eeprom data on page 244 , and section 16.8: flash write/ erase protection on page 243 modified section 16.7 on page 244 changed status of the do cument (datasheet inst ead of preliminary data)
revision history st72344xx st72345xx 246/247 doc id 12321 rev 5 22-sep-2008 3 document reformatted title modified removed references to st72340 devices and fastrom devices modified device summary on first page added note 1 and note 3 to table 3 on page 20 and removed note on iccdata and iccclk added note 5 and ?caution? to section 4.4 on page 28 added one caution to section 7.2 on page 42 modified note in section 7.3.3 on page 45 , added caution to section 7.5 on page 46 added one caution to section 7.6.2 on page 49 modified figure 24 on page 60 modified note 3 in output compare on page 99 added note to section 11.8.1 on page 185 modified table in table 84 on page 200 modified section 13.4 on page 204 : modified note 1 and added f rc values for v dd = 3 v modified table 94 on page 208 modified section 13.6.1 on page 210 modified emc characteristics on page 213 and removed references to dlu in absolute maximum ratings (electrical sensitivity) on page 214 modified section 13.10.1 on page 222 added note 2 to section 13.11.1 on page 224 added section 16.4 on page 242 section 16.4 on page 242 modified section 14 on page 227 (values in inches rounded to 4 decimal digits instead of 3 decimal digits) modified section 15 on page 232 , device ordering information on page 236 removed option list. 11-dec-2008 4 "flash write/erase protection? and ?in-application programming? removed in section 16: known limitations on page 239 (limitations corrected in the silicon revision now in production). updated section 14.1: ecopack on page 227 15-jun-2009 5 modified title of table 2 on page 16 added section 16.6: random read operations not supported with the standard i2c on page 244 table 126. document revision history (continued) date revision changes
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